Binary-to-BCD Conversion Using Reduced-Gate Doubler Logic
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Solution Overview
Problem
Existing methods for converting binary integers to binary coded decimals require complex logic flows and multiple logic gates, limiting the number of doubling operations that can be performed per clock cycle and thus impacting the performance of computer systems.
Innovation Solution
The proposed solution involves an intermediate format with an additional seventh bit for each digit to encode the inverse of the one weight, reducing the number of logic gates required for doubling operations and allowing more operations to be performed per clock cycle, using doubler logic that directly inputs the inverse one weight into AND gates and carrier/logic circuits to handle carry bits efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional binary integer to binary coded decimal conversion is used, then conversion accuracy is maintained, but the number of logic gates required increases and the number of doubling operations per clock cycle is limited
Solution Approach 1:
The patent segments the binary integer conversion process into multiple doubling stages, where each stage processes a portion of the bits. By dividing the conversion into discrete stages that can be pipelined, the system performs multiple doubling operations per clock cycle, thereby increasing productivity without requiring a proportional increase in total logic gates.
Solution Approach 2:
The patent employs dynamic logic circuits that can be reconfigured or activated selectively based on the current conversion stage and input data characteristics. This dynamic approach allows the same logic gates to serve multiple purposes across different clock cycles, increasing the effective number of operations per clock cycle while maintaining a compact gate count.
2Productivity
If more logic gates are used for conversion, then more doubling operations can be performed, but the device complexity and gate count increase
Solution Approach 1:
The patent prepares intermediate results and pre-computes certain values in advance during earlier clock cycles or initialization phases. By having partial results ready beforehand, the system can perform additional doubling operations in subsequent cycles without requiring additional logic gates, thus improving conversion speed while controlling complexity.
Solution Approach 2:
The patent designs logic gates that perform multiple functions depending on the operational phase and input conditions. The same gate structure is reused across different doubling stages and can handle various bit positions, reducing the total number of gates needed while maintaining high conversion throughput.
Data Source
AI summary
Reduced logic conversion of binary integers to binary coded decimals, including: generating, from an input binary integer, an intermediate value comprising all zero digits encoded in an intermediate format; until each bit of the input binary integer has been shifted into the intermediate value: shifting a bit of the input binary integer into the intermediate value; doubling the intermediate value; converting the intermediate value to a binary encoded decimal output; and wherein the intermediate format comprises, for each digit of the intermediate value, a plurality of bits corresponding to a plurality of even weights, a first bit corresponding to a one weight, and a second bit corresponding to an inverse of the one weight.