Logic Circuits Characterised By Logic Function TRIZ Cases

A temperature-driven refresh circuit varies rows per command to cut memory refresh current waste while meeting data hold time.

Using ternary full and half adders, this circuit processes three logic states to cut power consumption and reduce arithmetic circuit complexity.

Cross-coupled SR flip-flops use manufacturing variation to create stable random IC identifiers with low power and minimal hardware overhead.

Using feedback from both intermediate and end delay-line stages, this DLL clock circuit preserves pulse width and prevents clock switch-off.

Two matched delay loops improve single-edge delay measurement accuracy and reduce process fluctuation effects in ring oscillators.

A readable non-terminated bit line lets FPGA configuration latches save area while preserving data integrity during read and write operations.

By detecting the first pulse after preamble, the correction circuit fixes duty distortion and avoids delayed strobe recognition and re-reads.

A third transistor or capacitor holds the floating intermediate node near ground, limiting negative voltage stress in stacked transistor circuits.

Counter-based control and synchronized selection reduce clock-switching glitches, protecting clock edges and output accuracy.

Adjusts refresh command execution by process corner so memory rows meet hold-time limits while avoiding unnecessary refresh current.

Startup-activated clock paths remove the reference clock, enabling noise-insensitive glitch-free switching with lower power and chip area.

Time-encoded wavefronts and tunable delays enable temporal memory and computation, easing race-logic architecture design while improving efficiency.

By splitting a >1 GHz clock into lower-frequency paths, parallel counters avoid carry-delay errors and preserve accurate chip timing.

Parallel DRAM decoding splits bit-level and byte-level ECC to speed error correction while reducing hardware complexity and power use.

Stacking eDRAM above peripheral and compute circuits cuts footprint, latency, and power for encrypted in-memory computation.

Bypassing the PLL and divider before partial reset lowers clock frequency and current draw, helping SoCs avoid reset-time power faults.

Phase-inverted clock shaping and feedback delay reduce buffer use and prevent data collusion in cascaded latch transmission.

By merging latch and logic functions, this flip-flop circuit cuts signal delay, shrinks IC size, and speeds sequential logic operations.

Independent clocking lets separate multiplier arrays freeze unused logic, cutting multiplication power without adding extra circuit space.

An intermediate digit format with an inverse one-weight bit cuts doubling logic gates, enabling more binary-to-BCD stages per clock cycle.

A paired MTJ memory and determination circuit uses complementary and non-complementary states to encode ternary logic with less area overhead.

Bypassing the scan multiplexer from the critical data path preserves scan testability while reducing delay, area, and power overhead.

A clock-controlled debug unit lets registers sample only in valid clock periods, improving FPGA verification of chip clock gating.

Shared DBI and self-test judging circuitry cuts redundant memory readout hardware, lowering power and layout area while preserving error checks.

Generates full and empty FIFO status directly from read and write pointers, cutting synchronizer area, power, and timing-closure effort.

Independent control branches enable glitch-free switching from slower to faster clocks without deadlock or extra control clocks.

By mapping non-zero positions in sparse matrices, GPU logic avoids zero-element convolution work and improves matrix processing efficiency.

Phased clocks and tri-state feedback separate scan and data paths to cut setup time, preserve scan stability, and lower flip-flop power.

Queue scheduling separates read, arithmetic, and write paths in a PIM controller to cut memory-processor transfer bottlenecks in AI workloads.

Combining LOS and LFPS detector outputs enables accurate signal detection across power modes while reducing communication link energy use.

Cross-coupled inverters, transistors, and switches boost regeneration speed and sensitivity for resolving small high-speed input bits.

Two staged deglitcher delays absorb non-overlap timing, cutting driver delay while preserving glitch suppression and transistor separation.

A single-phase OAI/AOI latch array cuts complementary clocks and clock transistors to lower power while protecting stored data.

A shared latch handles both DRAM self-test and fuse-state storage, cutting chip area, simplifying control, and enabling synchronous testing.

Different threshold voltages in clock gating input and output stages reduce leakage current while maintaining clock tree performance.

Selective SPI switching lets multiple OIS modules share one gyroscope without access collisions, avoiding camera system exceptions and extra sensors.

Voltage-bias reconfiguration lets one homojunction logic unit perform multiple logic operations while cutting transistor count and power use.

A split adder computes power-of-two bits and carry-select remainder bits in parallel to avoid extra delay at non-power-of-two widths.

Ordered loop-thread execution with reenter queues and self-scheduling reconfiguration boosts throughput while improving energy efficiency.

Memristor gates with dynamic correction enable simultaneous forward and reverse logic, cutting NP computation time and resource growth.

Clock division, delay, and signal selection shape memory pulse width to balance faster access with reliable internal operation timing.

Carrier-envelope phase encoded light pulses generate summed currents in a probe structure, enabling logic operations far beyond electronic speed limits.

Direct MAC computation inside the memory array cuts data-transfer overhead and bit toggling, lowering power use in machine learning chips.

Logical AND/OR phase control aligns two outputs from one input across different clocks, enabling earlier rise timing and adjustable active width.

A 10-bit byte encoding adds an inversion flag and jumping edge so one link scheme supports both PLL and DLL transmission with correct recovery.

Dual reference voltages and programmable resistors detect high and low supply attacks early while compensating process drift to cut false alarms.

A biased or capacitively stabilized intermediate node prevents negative voltage stress in stacked transistors and reduces sub-threshold degradation.

Quarter-rate phase generation and rotation cut clock power while preserving accurate quadrature sampling for high-speed serial links.

By merging redundant clock-switching transistors, this complementary clock gate cuts flip-flop power and area while supporting low-voltage operation.

Shared read/write access transistors let pseudo-triple-port SRAM support simultaneous operations while preserving density and lowering power.