TSPC Latch Array Topology for Low-Clock-Power Data Storage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current latch arrays, such as transmission-gate-based flip-flops, consume significant power due to the requirement for complementary clocks and numerous clock transistors, making them inefficient for low-power applications like wireless communication devices.
Innovation Solution
The implementation of a true single phase clock (TSPC) based latch array using OR-AND-Inverter (OAI) and AND-OR-Inverter (AOI) gates, which eliminates the need for complementary clocks and reduces the number of clock transistors, thereby minimizing power consumption and transistor count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If transmission-gate-based flip-flops are used, then data storage functionality is achieved, but power consumption increases due to complementary clocks and numerous clock transistors
Solution Approach 1:
The patent extracts and eliminates the complementary clock signal requirement from the latch circuit. By using a single-phase clock signal instead of complementary clocks, the design removes the need for clock inversion circuits and reduces the number of clock transistors, directly addressing the power consumption issue while maintaining data storage functionality
Solution Approach 2:
The patent changes the clock signal parameter from dual-phase (complementary) to single-phase. This parameter change fundamentally alters the circuit operation, allowing the latch to function with fewer transistors and lower power consumption while achieving the same data storage purpose
2Reliability
If complementary clocks are used, then reliable clocking is achieved, but transistor count and power consumption increase
Solution Approach 1:
The patent removes the complementary clock requirement from the system, retaining only the essential single-phase clock signal. This extraction eliminates the power-consuming clock inversion process while maintaining sufficient clocking reliability for the latch operation through careful timing design
3Productivity
If traditional latch designs are used, then data storage is achieved, but power efficiency decreases
Solution Approach 1:
The patent changes the fundamental operating parameter from dual-clock to single-clock operation. This parameter change reduces dynamic power consumption proportional to the reduction in switching activity, while the latch maintains full data storage capability through its cross-coupled gate structure
Solution Approach 2:
By extracting and removing the complementary clock signals and associated inversion circuitry, the patent eliminates a major source of power consumption while preserving the essential data storage function through the optimized latch structure
Data Source
AI summary
A latch array including a row of master latches coupled to columns of slave latches. Each master latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch an input data, and each slave latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch the data from the master latch, and an inverter including an input coupled to the AOI gate and an output to produce an output data based on the input data. Alternatively, each master latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch an input data, and each slave latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch the data from the master latch, and an inverter including an input coupled to the OAI gate and an output to produce an output data.