SR Flip-Flop PUF Circuit for Low-Power IC Authentication
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Solution Overview
Problem
Existing security solutions for integrated circuits (ICs) face challenges such as overproduction, counterfeiting, and authentication, particularly in resource-constrained IoT devices, where cryptography algorithms are difficult to deploy effectively due to recent attacks and environmental variations.
Innovation Solution
A novel SR Flip-Flop (FF) based Physical Unclonable Function (PUF) design that leverages manufacturing process variations to generate unique challenge-response pairs, utilizing cross-coupled NAND-based SR-FFs and existing SR-FFs in ICs without additional hardware, to provide low-cost, tamper-evident, and reproducible authentication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cryptographic algorithms are deployed for authentication, then security authentication capability is improved, but resource consumption and complexity increase making them unsuitable for resource-constrained IoT devices
Solution Approach 1:
The patent extracts the security authentication function from complex cryptographic algorithms and implements it using simple SR flip-flop circuits that leverage inherent manufacturing variations. This extracts the essential authentication capability while removing the computational complexity burden.
Solution Approach 2:
The SR flip-flop based PUF generates authentication keys using inherent manufacturing variations and process noise that are already present in the device. The system uses its own physical characteristics to generate security credentials without requiring external cryptographic processing resources.
2Reliability
If cryptographic algorithms are deployed for authentication, then security authentication capability is improved, but power consumption and computational overhead increase
Solution Approach 1:
The patent uses inexpensive SR flip-flop circuits that consume minimal power to generate authentication credentials. These simple digital circuits replace power-intensive cryptographic processors, providing security through low-cost, low-power physical variations rather than computational expense.
3Device complexity
If standard SR flip-flops are used, then circuit simplicity is maintained, but vulnerability to key-guessing attacks increases
Solution Approach 1:
The patent introduces asymmetry into the SR flip-flop circuit by deliberately creating mismatched cross-coupled paths with different delay characteristics. This asymmetric design ensures that the internal state transitions depend on unique physical variations, making the system resistant to attacks while maintaining circuit simplicity.
Solution Approach 2:
The patent changes the physical parameters of the SR flip-flop circuit by introducing controlled delays and mismatches in the cross-coupled paths. These parameter variations create unique challenge-response behaviors that prevent key-guessing attacks while keeping the basic flip-flop structure intact.
4Stability of the object's composition
If cross-coupled paths with equal delays are used, then circuit symmetry is maintained, but PUF response uniqueness and security are reduced
Solution Approach 1:
The patent deliberately breaks circuit symmetry by creating cross-coupled paths with unequal delays. This asymmetry is essential for generating unique PUF responses, as it ensures that each flip-flop has a distinct internal state transition characteristic based on its physical variations, thereby enhancing security.
Data Source
AI summary
The present disclosure presents various systems and methods for implementing a physical unclonable function device. One such method comprises providing an integrated circuit having a plurality of set/reset flip flop logic circuits, wherein each of the set/reset flip flop logic circuits enters a metastable state for a particular input sequence. The method includes varying circuit parameters for each of the plurality of set/reset flip flop logic circuits to account for manufacturing variations in the set/reset flip flop logic circuits and enable generating a stable but random output in response to the particular input sequence. Thus, by applying the particular input sequence to the integrated circuit, a unique identifier for the integrated circuit can be derived from an output response of the plurality of set/reset flip flop logic circuits.