CMOS Clock Generation Circuit With Phase Rotation and Frequency Doubling
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Solution Overview
Problem
High-speed serial communication links in electronic devices face challenges with power consumption due to the use of multiple increased frequency clock signals, which can lead to errors in data reception due to phase relationships and variations in clock signal phases.
Innovation Solution
A low-power clock generation circuit that generates multiple sampling clocks at different phases using a phase generator, phase rotator, frequency doubler, and quadrature clock generation circuit, implemented in CMOS circuits to reduce power consumption and manage phase relationships effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple high-frequency clock signals are used for timing control in high-speed serial links, then timing precision and data transmission speed are improved, but power consumption increases
Solution Approach 1:
The clock generation circuit is segmented into multiple functional blocks (phase generator, phase rotator, frequency doubler, quadrature clock generation circuit) that operate at different frequencies. The phase generator and phase rotator operate at quarter-rate frequency, while only the frequency doubler and quadrature clock generation circuit operate at half-rate frequency. This segmentation allows critical timing functions to be performed at lower frequencies, reducing overall power consumption while maintaining high-speed data transmission capability.
2Reliability
If multiple clock signals with different phases are generated to control SERDES operation, then timing accuracy and data recovery reliability are improved, but circuit complexity increases
Solution Approach 1:
The patent combines multiple clock generation functions into a single integrated circuit. The phase generator, phase rotator, frequency doubler, and quadrature clock generation circuit are merged into one unified structure that generates all required phase-shifted clock signals (0°, 90°, 180°, 270°) from a single input clock signal. This merging reduces the number of separate components and simplifies the overall system architecture while maintaining the ability to provide precise phase control for reliable data recovery.
Solution Approach 2:
The clock generation circuit is designed as a universal multi-functional unit that can generate multiple phase-shifted clock signals simultaneously. The phase rotator can adjust phase shifts dynamically, and the frequency doubler can operate with different input phases to produce the required quadrature clock signals. This multi-functionality allows a single circuit to replace what would traditionally require multiple separate clock generators, reducing complexity while maintaining reliability.
Data Source
AI summary
A low-power clock generation circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts, a phase rotator circuit that outputs phase-adjusted clock signals, a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference, and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.