Clock Gating Cell Stages With Different Threshold Voltages
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Clock gating cells with a single low voltage threshold induce high power consumption due to increased leakage current, which is not efficiently managed in existing clock tree designs.
Innovation Solution
A clock gating cell design that operates with multiple voltage thresholds, where the input stage and output stage utilize different voltage thresholds, allowing for reduced leakage current and improved power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a low voltage threshold is used in clock gating cells, then the clock tree performance is improved, but the leakage current increases causing high power consumption
Solution Approach 1:
The clock gating cell is divided into multiple stages (first input stage, second input stage, output stage), each operating at different voltage thresholds. This segmentation allows different parts of the circuit to be optimized for different functions: faster response where needed and lower leakage where possible.
Solution Approach 2:
Different voltage thresholds are applied to different stages of the clock gating cell based on their specific functional requirements. The first input stage uses a first voltage threshold, the second input stage uses a second voltage threshold, and the output stage uses a third voltage threshold, allowing each stage to operate optimally for its specific purpose.
2Device complexity
If a single voltage threshold is used in all stages, then the design is simple, but the power consumption is high due to increased leakage current
Solution Approach 1:
The voltage threshold parameter is changed across different stages of the clock gating cell. By varying the voltage threshold from one stage to another (first voltage threshold in first input stage, second voltage threshold in second input stage, third voltage threshold in output stage), the circuit achieves better power-performance tradeoff without requiring complete redesign.
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
A clock gating cell (1) is provided. The clock gating cell (1) includes an input stage (20) and an output stage (11). The input stage receives a first clock signal (CK) and at least one input enable signal (CEN) and generates a first enable signal (ENL) corresponding to one of the least one input enable signal according to the first clock signal. The output stage (11) is coupled to the input stage (10). The output stage receives the first enable signal and the first clock signal and generates a clock gating signal (ENCK) according to the first enable signal and the first clock signal. The input stage operates based on a first voltage threshold, and the output stage operates based on a second voltage threshold. The first voltage threshold is different from the second voltage threshold.