Stacked Transistor Circuits With Intermediate Node Bias Control
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Solution Overview
Problem
In stacked transistor configurations, the intermediate node can float, leading to negative voltages due to parasitic capacitance, causing non-conductive stress and potential transistor degradation as the drain-to-source voltage exceeds the supply voltage while the transistor operates in the sub-threshold region.
Innovation Solution
Incorporating a third transistor to bias the intermediate node to ground or connecting a capacitor to the intermediate node to reduce negative voltages, either by using a PMOS transistor connected to the supply voltage or a capacitor to limit charge coupling from the gate to the intermediate node.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the intermediate node is left floating in stacked transistor configurations, then the circuit structure remains simple, but negative voltages develop due to parasitic capacitance causing transistor degradation
Solution Approach 1:
A third transistor is introduced as an intermediary component connected to the intermediate node between the first and second transistors. This intermediary transistor actively controls the voltage at the intermediate node, preventing it from floating and developing negative voltages that would cause stress on the stacked transistors.
Solution Approach 2:
The third transistor is configured to preemptively maintain the intermediate node voltage within safe operating limits before negative voltages can develop. By continuously biasing the intermediate node, the circuit prevents the harmful voltage conditions rather than reacting to them after they occur.
2Reliability
If a third transistor is added to bias the intermediate node, then transistor degradation is prevented, but device complexity increases
Solution Approach 1:
The third transistor is designed to perform multiple functions simultaneously: it biases the intermediate node to prevent negative voltages, controls the voltage level based on the operational state of the stacked transistors, and integrates seamlessly with the existing circuit topology. This multi-functionality justifies the added component by providing comprehensive protection and control.
Solution Approach 2:
The invention changes the voltage parameter at the intermediate node by introducing the third transistor, which actively maintains the voltage within safe operating limits. This parameter control transforms the intermediate node from a floating, unpredictable voltage point to a controlled, stable voltage point, preventing transistor stress.
3Device complexity
If the intermediate node voltage is allowed to float, then device complexity remains low, but the drain-to-source voltage exceeds supply voltage causing stress
Solution Approach 1:
The third transistor serves as a protective intermediary between the power supply and the intermediate node, controlling the voltage levels to prevent harmful conditions. It mediates the voltage distribution in the stacked transistor configuration, ensuring that no transistor experiences excessive drain-to-source voltage.
Solution Approach 2:
The third transistor applies preliminary counter-action by maintaining the intermediate node voltage within safe limits before harmful voltage conditions can develop. It preemptively prevents the drain-to-source voltage from exceeding the supply voltage by actively controlling the intermediate node potential.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents the intermediate node voltage from becoming negative, reducing the risk of transistor degradation by maintaining the drain-to-source voltage within safe limits and ensuring reliable operation.
Implementation Method 1
a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node
Data Source
AI summary
A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is connected to the second current terminal at an intermediate node and the fourth current terminal connected to a ground or supply node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.