Integrated Deglitcher Circuit With Non-Overlap Timing for Faster Drivers
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Solution Overview
Problem
Conventional output drivers experience significant signal propagation delay due to both deglitcher and nonoverlap blocks, which cannot be reduced without allowing unwanted glitches or compromising performance.
Innovation Solution
The integration of nonoverlap delay into the deglitcher delay, utilizing two deglitcher circuits with distinct delays (tDLY1 and tNOL) that combine to provide the original deglitcher time, allowing for reduced total driver delay without affecting performance, by using RC circuits to control edge delays and ensure transistor non-overlap.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the deglitcher delay is reduced to increase driver speed, then the driver delay decreases and speed improves, but unwanted glitches will pass through the driver and performance deteriorates
Solution Approach 1:
The patent segments the delay function into two separate circuits: a first deglitcher circuit that provides glitch suppression with a first delay, and a second deglitcher circuit that provides additional delay with a second delay. This segmentation allows each circuit to be optimized for its specific function while working together to achieve both speed and reliability.
Solution Approach 2:
The patent combines the outputs of two separate deglitcher circuits to produce the final driver output. The first deglitcher circuit handles glitch suppression while the second provides additional delay, and their combined effect achieves both fast switching and reliable glitch suppression without compromising either performance metric.
2Reliability
If separate deglitcher and nonoverlap blocks are used to ensure proper transistor timing, then transistor non-overlap is ensured, but total driver delay increases significantly
Solution Approach 1:
The patent merges the nonoverlap delay function into the second deglitcher circuit. The second deglitcher circuit simultaneously provides both the additional delay needed for glitch suppression and the nonoverlap timing for transistor control. This integration eliminates the need for a separate nonoverlap block, reducing total driver delay while maintaining reliable transistor timing.
Solution Approach 2:
The second deglitcher circuit is designed to serve multiple functions: it provides delay for glitch suppression, ensures proper nonoverlap timing between transistors, and generates the mode control signal. This multi-functionality reduces the overall circuit complexity and total delay compared to having separate dedicated blocks for each function.
3Device complexity
If a single deglitcher circuit is used instead of two separate circuits, then device complexity is reduced, but the ability to provide both glitch suppression and nonoverlap delay is compromised
Solution Approach 1:
The patent combines two deglitcher circuits in a way that reduces overall complexity compared to having separate deglitcher and nonoverlap blocks. The second deglitcher circuit's output feeds back to control the mode of the first deglitcher circuit, creating an integrated system that provides both glitch suppression and nonoverlap timing with coordinated operation.
Solution Approach 2:
The second deglitcher circuit's output is coupled back to control the mode control signal of the first deglitcher circuit. This feedback mechanism allows the two circuits to work together cooperatively, with the second circuit's delay output determining the operational mode of the first circuit, thereby achieving both glitch suppression and nonoverlap timing through their interaction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the total driver delay while maintaining original deglitching and non-overlap performance, ensuring transistors M1 and M2 do not operate simultaneously, thus enhancing signal propagation efficiency.
Implementation Method 1
utilizing two deglitcher circuits with distinct delays (tDLY1 and tNOL) that combine to provide the original deglitcher time, allowing for reduced total driver delay without affecting performance, by using RC circuits to control edge delays
Data Source
AI summary
A driver circuit includes a first deglitcher circuit that delays a rising edge or a falling edge of an input signal according to a mode control signal and supplies a first output signal. A second deglitcher circuit receives the first output signal and delays either a rising edge or a falling edge of the first output signal by a second delay according to the mode control signal and supplies a second output signal. Logic gates combine the first and second output signals to supply gate control signals for output transistors to drive the driver circuit output. A sum of the first delay and the second delay determines the total deglitch time defining a pulse width of pulses that are suppressed by the driver circuit and the second delay determines a non-overlap time. The non-overlap time overlaps in time with the total deglitch time.