Parallel Clock Multiplexer for Glitch-Free Fast Clock Switching
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Solution Overview
Problem
Existing clock multiplexer devices face issues with glitches and deadlocks when switching from a slower clock signal to a faster one, due to their serial circuit architecture, and require independent additional clocks.
Innovation Solution
A clock multiplexer device with control circuitry that generates enable signals and determines output clock signals based on selection signals with opposite logic values, allowing seamless switching between clock signals without relying on slower clock rates and avoiding deadlocks, utilizing OR gate and NAND/AND gate circuits to manage signal transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronizer circuits are coupled in series to sequentially process multiple clock signals, then glitch-free output is achieved, but the clock multiplexer is limited by the slower clock signal and requires additional independent clocks
Solution Approach 1:
The patent divides the clock multiplexer into two independent parallel branches (first control circuitry and second control circuitry), each processing one clock signal independently. This segmentation eliminates the serial dependency where the slower clock limited the overall operation, allowing each branch to operate at its own clock rate without being constrained by the other branch.
Solution Approach 2:
The patent transitions from a serial time-based processing architecture to a parallel spatial architecture by introducing two independent control circuitries that operate simultaneously. The selection between clock signals is achieved through enable signals and output circuitry rather than sequential switching, adding a dimensional shift from time-sequential to space-parallel operation.
2Ease of operation
If additional independent clocks are used to control switching, then switching control is achieved, but device complexity and resource requirements increase
Solution Approach 1:
The patent makes the existing clock signals (CLK0 and CLK1) serve dual functions: they are both the clock signals to be selected and the control signals for switching. The clock signals themselves generate the enable signals through their interaction with selection signals, eliminating the need for separate independent control clocks. This multi-functionality reduces resource requirements while maintaining switching control capability.
Solution Approach 2:
The clock signals and selection signals work together to automatically generate the enable signals that control the switching operation. The system uses its own internal signals (CLK0, CLK1, SEL) to control the switching process without requiring external independent control clocks, achieving self-service operation.
3Speed
If the clock multiplexer switches from a slower clock signal to a faster clock signal, then higher output frequency is achieved, but deadlock occurs when the slower clock or independent control clock stops
Solution Approach 1:
By segmenting the control into two independent parallel branches, the patent eliminates the deadlock vulnerability of the serial architecture. When switching from a slower to a faster clock signal, the target clock's branch operates independently and can immediately output the faster clock signal without waiting for or being constrained by the source clock signal, thus avoiding deadlock.
Solution Approach 2:
The patent prepares both clock signal paths in advance with their respective control circuitries ready to operate. When switching is needed, the enable signals are generated to activate the target clock path while deactivating the source path, allowing seamless transition to the faster clock signal without waiting for the slower clock to complete cycles, thereby preventing deadlock.
Data Source
AI summary
A clock multiplexer device includes first and second control circuitries and an output circuitry. The first control circuitry generates a first enable signal and a first signal according to a first clock signal and a first selection signal, and determines whether to output the first signal to be a first output clock signal according to a second selection signal and a second enable signal. The first and the second selection signals have opposite logic values. The second control circuitry generates the second enable signal and a second signal according to a second clock signal and the second selection signal, and determines whether to output the second signal to be a second output clock signal according to the first selection signal and the first enable signal. The output circuitry outputs one of the first output clock signal and the second output clock signal to be a final clock signal.