Clock Multiplexer Circuitry for Glitch-Free Clock Switching
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Solution Overview
Problem
Clock multiplexer circuitry introduces glitches when switching between different clock signals, leading to errors that can misinterpret clock edges and incorrectly enable or disable circuit elements, affecting the performance of electronic devices.
Innovation Solution
The proposed clock multiplexer circuitry includes multiple paths with selection circuitry, counter circuitry, and output logic to generate a glitch-free clock signal, using techniques such as sampling and flip-flop synchronization to mitigate errors during transitions between clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiplexer circuitry is used to select among multiple clock signals, then clock source flexibility is improved, but glitches are introduced in the output when switching between clock signals
Solution Approach 1:
The patent applies preliminary action by using counter circuitry to generate control signals that anticipate and prepare for clock signal transitions. The counters are clocked by the input clock signals and generate selection control signals before the actual multiplexer switching occurs, ensuring that the output clock signal transitions smoothly without glitches when switching between different clock sources.
2Device complexity
If simple multiplexer circuitry is used for clock selection, then device complexity is reduced, but glitches occur during clock signal transitions
Solution Approach 1:
The patent introduces intermediary counter circuitry between the input clock signals and the multiplexer control inputs. These counters act as mediators that translate the input clock signals into synchronized selection control signals, preventing direct glitches from propagating to the output while maintaining a relatively simple overall circuit structure.
3Speed
If clock switching is performed without synchronization, then switching speed is improved, but errors occur in the output clock signal
Solution Approach 1:
The patent implements feedback mechanisms where the counter circuitry continuously monitors the input clock signals and uses their actual timing information to generate the selection control signals. This feedback approach ensures that clock switching occurs at the correct moments synchronized with the input clock edges, preventing output errors while maintaining fast switching speeds.
Data Source
AI summary
Clock multiplexer circuitry outputs one of a first or second clock signal. First selection circuitry is connected in series with first counter circuitry. The first selection circuitry and the first counter circuitry receive a first clock signal and a first selection signal. A first control signal is generated based on the first clock signal and the first selection signal. Second selection circuitry is connected in series with second counter circuitry. The second selection circuitry and the second counter circuitry receive a second clock signal and a second selection signal. A second control signal is generated based on the second clock signal and the second selection signal. The output circuitry is connected to the first counter circuitry and the second counter circuitry. The output circuitry outputs one of the first clock signal and the second clock signal based on the first control signal and the second control signal.