Temporal State Machine Architecture Using Time-Encoded Wavefronts

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Solution Overview

Problem

Current computational architectures have stagnated due to limitations in transistor design and performance, and the adoption of race logic encoding schemes has been hindered by the lack of practical, systematized methods for building computer architectures that utilize temporal encoding.

Innovation Solution

The development of temporal memory and computational circuit components that utilize tunable delay components and race logic to encode data in the timing of electrical signals, allowing for the implementation of temporal state machines and computational units that perform operations in the time domain.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional digital clocked schemes are used for storing data and performing operations, then computational components can operate reliably with well-established transistor design, but progress in improving computational performance has stagnated due to transistor design limitations

Engineering Contradiction:
Improvecomputational performanceVSAvoidtransistor design complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent replaces the traditional digital clocked computational system with a temporal encoding system that uses arrival time of signals rather than clock cycles. This substitution fundamentally changes the computational paradigm from time-discrete clocked operations to continuous time-domain operations, enabling improved computational performance without being constrained by transistor switching speed limitations

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the encoding parameter from voltage level (0 and 1) to arrival time of signals. By encoding data in the temporal domain rather than voltage domain, the system can achieve higher computational density and performance while using existing transistor technology, effectively decoupling performance improvements from transistor design advances

Inventive Principle:
Principle #35Parameter changes

2Productivity

If race logic encoding schemes are adopted to improve computational efficiency, then energy efficiency and computational speed can be enhanced, but practical implementation has been hindered by the lack of systematized methods for building computer architectures

Engineering Contradiction:
Improvecomputational efficiencyVSAvoidarchitectural implementation ease
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The patent segments the computational architecture into distinct functional units including temporal memory, computational units, and interconnect structures. Each unit is designed to handle temporal encoding specifically, making the overall system easier to implement by breaking down the complex architecture into manageable, specialized components

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent creates universal building blocks such as temporal memory units and computational units that can be configured for different applications. These multi-functional components can implement various operations (AND, OR, NOT, etc.) using the same temporal encoding mechanism, simplifying the manufacturing and deployment process

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Loss of energy

If multiple bits are encoded on a single wire using arrival time encoding, then energy consumption is reduced and computational simplicity is improved, but the complexity of decoding and synchronization increases

Engineering Contradiction:
Improveenergy consumptionVSAvoiddecoding complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent employs self-synchronizing mechanisms where the temporal encoding scheme inherently provides synchronization information through the arrival times themselves. The system uses the relative timing of signal arrivals to automatically synchronize operations without requiring external clock signals or complex synchronization circuits, thereby reducing decoding complexity despite multi-bit encoding

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11817173B2Timing-based computer architecture systems and methods
Publication Date: 2023.11.14 THE GOVERNMENT OF THE UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY DEPARTMENT OF HEALTH & HUMAN SERVICES
  • US11817173B2 patent drawing
  • US11817173B2 patent drawing
  • US11817173B2 patent drawing

AI summary

Systems and methods are provided herein that implement and utilize temporal state machines and other temporal computational/memory circuits. For example, a temporal state machine is provided that comprises a temporal computational unit comprising at least one circuit to perform a time-domain operation, and a temporal memory unit. Both the temporal computational unit and temporal memory unit can operate using solely, or partially, time-encoded wavefronts. The computation unit accesses time-encoded wavefronts from the memory and can output and write time-encoded wavefronts back to the memory.