Configuration Memory Latch With Readable Non-Terminated Bit Line
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Solution Overview
Problem
The semiconductor industry faces challenges in designing programmable logic devices like FPGAs due to difficulties in incorporating desired logic within specified die size, routing signals, and ensuring signal stability, particularly with the use of SRAM cells which are foundry and process dependent, and the inefficiency of registers as storage elements.
Innovation Solution
The implementation of a configuration memory latch circuit using a word line write signal, a word line read signal, a non-terminated bit line, transmission gates, a NAND gate, an inverter, a pull-down network, and a sensing block to enable efficient data storage and retrieval, allowing latches to be used as storage elements, thereby facilitating area-efficient FPGA design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If SRAM cells are used as storage elements, then area efficiency is improved, but foundry and process dependency increases causing migration difficulties
Solution Approach 1:
The patent changes the fundamental parameter of storage element type from SRAM cells to latches. This parameter change allows the design to achieve area efficiency while simultaneously reducing foundry and process dependency, as latches have more predictable timing characteristics across different manufacturing processes compared to SRAM cells
2Area of moving object
If latches are used as storage elements, then area efficiency is improved, but reading difficulties arise
Solution Approach 1:
The patent introduces a pull-down network as an intermediary mechanism between the latch storage element and the read operation. This pull-down network actively drives the bit line during reads, mediating the reading process to overcome the inherent reading difficulties of latches while preserving their area efficiency benefits
3Ease of manufacture
If registers are used as storage elements, then ease of implementation is improved, but area efficiency deteriorates
Solution Approach 1:
The patent changes the storage element parameter from registers to latches, fundamentally altering the timing and control characteristics. This parameter change enables area-efficient design while the pull-down network and controlled read mechanism address the implementation complexity, achieving a better balance than traditional register-based approaches
Data Source
AI summary
An area efficient readable and resettable configuration memory latch is disclosed that maintains latch data integrity through read and write operations and includes a non-terminated inout bit line (BL). During write operations, enabled by a Word Line Write (WLW) signal, the non-terminated inout BL drives data to be written, while, during read operations, enabled by a Word Line Read (WLR) signal, the state of the BL is indicative of a data stored in the latch. A pull-down network is activated when the WLR signal is asserted and the stored data is logic one and, when activated, operates to pull down the BL to logic zero; the pull-down network is inactive otherwise. A weak pull-up operates to pull up the BL when the pull-down network is inactive. A sensing block is configured to sense the state of the BL when the WLR signal and a read enable signal are both asserted.