Master-Slave Flip-Flop with Phased Clock Feedback Paths
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Solution Overview
Problem
Existing flip-flop circuits in high-performance microprocessors face challenges in reducing setup and hold times, clock-to-output times, and power consumption, while maintaining stable data signal input speeds and scan input signal paths.
Innovation Solution
The design incorporates a master latch, slave latch, and clock generator with independent scan and data paths, utilizing tri-state inverters and AOI circuits to optimize clock signals and reduce operation delays, allowing for faster data latch operations and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the scan path and data path are combined in a single input path, then the circuit complexity is reduced, but the data input speed and scan input signal stability cannot be optimized simultaneously
Solution Approach 1:
The patent divides the input path into two independent paths: a scan path for scan input signals and a data path for data signals. This segmentation allows each path to be optimized independently for its specific function, enabling faster data input speed while maintaining scan signal stability without requiring a single complex multiplexed path.
2Loss of time
If the clock signal is applied directly to the latch circuit, then the clock-to-output time is minimized, but the setup and hold times cannot be reduced further
Solution Approach 1:
The patent introduces a clock delay circuit that applies a delayed version of the clock signal to the latch circuit. This preliminary delay action allows the data signal to be fully stabilized and latched before the clock edge arrives, thereby reducing setup and hold times while maintaining an optimized clock-to-output time through the buffered clock path.
3Productivity
If the flip-flop operates at maximum clocking speed, then the logic clocking speed is maximized, but power consumption increases when the flip-flop is inactive
Solution Approach 1:
The patent implements a power management mechanism that periodically controls the operation of the latch circuit based on activity detection. When the flip-flop is inactive (not switching), the circuit enters a low-power state by disabling unnecessary signal paths, thereby reducing power consumption while maintaining the capability to operate at maximum clocking speed when data switching is required.
Data Source
AI summary
A flip-flop circuit includes a clock generator configured to generate first and second clock signals having different phases relative to each other, and a master-slave latch circuit including master and slave latches. The master latch includes a scan path configured to output a scan path signal in response to a scan enable signal and a scan input signal, and a data path configured to output a first latch signal in response to a data signal and the scan path signal. A feedback path is provided, which includes a tri-state inverter responsive to the first and second clock signals. The tri-state inverter has an input terminal connected to an output terminal of the data path and an output terminal connected to a node of the scan path.