Shared Latch Circuit for DRAM Self-Test and Fuse Storage
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Solution Overview
Problem
Conventional DRAM chips require a large number of latches, which occupy significant chip area and increase the size of the chip, as they are used to store states of fuse or antifuse devices and self-test signals.
Innovation Solution
A latch circuit comprising a latch module, a set control module, a reset control module, and a clock module, where the self-test enable signal determines the operation mode, allowing the latch circuit to output high-level signals for testing and read/write data in normal operation, thereby reducing the number of latches needed and simplifying the circuit structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a large number of latches are used to store states of fuse devices and self-test signals, then the storage capability is improved, but the chip area increases significantly
Solution Approach 1:
The patent combines the self-test latch and fuse latch into a single shared latch circuit. The latch module can be controlled to perform different functions (self-test mode or fuse state storage mode) through control signals, eliminating the need for separate latches for each function and thereby reducing chip area while maintaining full storage capability
Solution Approach 2:
The shared latch circuit is designed to be multi-functional, capable of operating in different modes (self-test mode and normal operation mode) based on control signals. This universal latch structure replaces multiple specialized latches, achieving the same storage capability with reduced hardware resources and smaller chip area
2Adaptability or versatility
If separate latches are used for self-test signals and fuse devices, then the testing function is improved, but the circuit complexity increases
Solution Approach 1:
The patent merges the self-test control circuit and fuse control circuit into a unified control structure. The latch module shares common control inputs (SET, RESET, CLK) and data input, with mode selection achieved through logical control rather than separate physical circuits, thereby maintaining testing functionality while reducing overall circuit complexity
Solution Approach 2:
The control modules are designed with universal control capabilities that can switch between self-test mode and normal operation mode. The set control module and reset control module can selectively control the latch based on the operational mode, providing adaptable testing function without requiring separate dedicated control circuits for each mode
Data Source
AI summary
A latch circuit includes a latch module, a set control module, a reset control module and a clock module, wherein the latch module is employed for latching data input by a data module, the set control module is employed for controlling the latch module to output a high-level signal, the reset control module is employed for controlling the latch module to output a low-level signal, and the clock module is employed for providing a readout clock signal to the latch module.