Clock Bypass Logic for Low-Power Partial Reset in SoCs
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Solution Overview
Problem
Infotainment system-on-a-chip (SoC) experiences high power consumption during partial reset, leading to potential power faults and non-compliance with customer specifications due to increased power consumption during reset intervals, which is 1.5 to 4 times higher than in functional mode.
Innovation Solution
The integration of clock management logic with PLL and divider bypass mechanisms combined with delay logic to reduce current levels during partial reset by reducing clock rates from gigahertz to megahertz range and using staggered bypass control signals to bypass PLLs and dividers before initiating a partial reset.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a partial reset is performed in a synchronous reset mechanism, then the reset function is achieved, but power consumption increases 1.5 to 4 times compared to functional mode
Solution Approach 1:
The patent applies preliminary action by bypassing the PLL and divider circuits before the reset signal is actually applied to the clock domains. The bypass logic is activated in advance to switch the clock path from the PLL-divider chain to a direct reference clock path, reducing power consumption before the reset operation begins. This ensures that when reset occurs, the high-power PLL and divider circuits are already in a low-power state.
Solution Approach 2:
The patent implements dynamics by making the clock path configurable and switchable between two modes: normal operation mode (through PLL and divider) and reset mode (direct reference clock through bypass logic). The system dynamically transitions between these modes based on the reset state, allowing optimal power consumption characteristics for each operational phase while maintaining reset functionality.
2Reliability
If clock domains operate at high frequency during reset, then reset timing is maintained, but power consumption exceeds customer specifications
Solution Approach 1:
The patent applies local quality by providing different clock paths for different operational conditions within the same clock domain infrastructure. During normal operation, the full PLL-divider chain provides high-frequency clocks. During reset, the bypass logic provides a simplified direct path from reference clock to clock domain, maintaining necessary timing while reducing power consumption locally in the affected clock paths.
Solution Approach 2:
The patent changes the clock signal parameters (frequency and path) based on the reset state. By switching from the PLL-generated high-frequency clock through dividers to a direct reference clock path during reset, the system modifies the clock parameters to achieve lower power consumption while preserving the essential reset timing requirements.
Data Source
AI summary
An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The bypass logic selectively bypasses the PLL and divider responsive to a bypass control signal triggered by a reset signal. The reset signal also triggers a reset control signal delayed relative to the bypass control signal.