Logic-Embedded Flip-Flop Circuit for Lower Signal Delay
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Solution Overview
Problem
As integrated circuits (ICs) become more sophisticated, the delay time for output from sequential circuits to combinational logic circuits and vice versa increases with the number of logical operations performed, leading to inefficiencies in data processing speed.
Innovation Solution
A dynamic sequential circuit with a logic embedded latch circuit and flip-flop design that shares circuit structures for logical operations and latching functions, using multiple circuits and inverters to determine output logic levels based on input signals and clock signals, reducing the size and operation time of the IC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of logical operations in combinational logic circuit increases, then the functionality and sophistication of IC improves, but the delay time for signal transmission between sequential circuits increases
Solution Approach 1:
The patent merges the latch circuit and logic circuit into a single integrated structure where the latch circuit shares its internal nodes (first and second output nodes) with the logic circuit. This integration eliminates the need for separate signal transmission paths between latch and logic circuits, thereby reducing delay time while maintaining enhanced functionality through the combined structure.
Solution Approach 2:
The latch circuit is designed to serve multiple functions: it acts as both a data storage element (latch functionality) and as part of the logic computation structure. The first and second output nodes of the latch circuit are directly utilized by the logic circuit for logical operations, making the latch circuit a multi-functional component that reduces overall circuit complexity and signal transmission delay.
2Device complexity
If separate latch circuit and logic circuit structures are used, then the design is simple and modular, but the IC size and operation time increase
Solution Approach 1:
The patent combines the latch circuit and logic circuit into a unified structure where the latch circuit's output nodes are directly connected to and shared with the logic circuit inputs. This merging reduces the number of separate components and interconnections, thereby decreasing IC size and reducing the time required for operations while maintaining design clarity through systematic integration.
Data Source
AI summary
An integrated circuit includes a first circuit, a second circuit, and an inverter. The first circuit receives a first input signal, an inverted clock signal, a first logic level of a first output node, and a logic level of a second output node to determine a second logic level of a first output node. The second circuit receives the first input signal, the clock signal, the first logic level, and the second logic level to determine a logic level of the second output node. The inverter receives a second input signal to output the inverted second input signal to the first circuit or the second circuit. A logic level of the first output node or a logic level of the second output node is output as an output signal when a logic level of the clock signal is a first logic level.