Memory Pulse Generation Circuit Using Clock Division and Delay
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current pulse signal generation circuits for memories, especially with higher performance and smaller size requirements, face challenges in controlling the effective level width of pulse signals, which affects access speed and internal operations, as the constrained width fails to meet the demands of faster storage speeds and smaller process nodes.
Innovation Solution
A pulse signal generation circuit comprising a clock frequency division component, a time delay component, and a selection component, where the clock frequency division component reduces the clock signal frequency, the time delay component generates a time delay signal based on the clock frequency division signal, and the selection component selects the pulse signal based on preset conditions to achieve a suitable effective level width, ensuring the pulse signal meets the requirements of a synchronous circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the pulse width is made wider to ensure internal operations are completed, then the reliability of internal operations is improved, but the access speed of the memory decreases
Solution Approach 1:
The pulse generation circuit dynamically adjusts the pulse width based on operational requirements. The circuit uses a clock frequency division component and a time delay component that can be configured to produce different pulse durations, allowing the system to optimize between speed and reliability depending on the specific memory operation being performed.
Solution Approach 2:
The invention changes the temporal parameters of the pulse signal by introducing a time delay component that can adjust the pulse width. By modifying the delay parameter in the time delay component, the circuit generates pulse signals with different effective levels, enabling flexible control over both access speed and internal operation completion.
2Speed
If the pulse width is made narrower to increase access speed, then the speed of memory access is improved, but the internal operations of the memory cannot be completed
Solution Approach 1:
The circuit provides dynamic pulse width adjustment capability through the time delay component, which can be configured to generate appropriately wide pulses for different internal operations while maintaining high access speeds when possible. This dynamic adaptation allows the system to achieve narrow pulses when operations are simple and wider pulses when operations require more time.
Solution Approach 2:
The time delay component enables parameter changes in the pulse signal by adjusting the delay time, which directly controls the pulse width. This parameter adjustment mechanism allows the circuit to optimize pulse duration for each specific access operation, achieving high speed when narrow pulses suffice and ensuring operation completion when wider pulses are needed.
3Device complexity
If a fixed pulse generation method is used, then the circuit complexity is reduced, but the adaptability to different access performance requirements is limited
Solution Approach 1:
The pulse generation circuit achieves multi-functionality by combining a clock frequency division component with a time delay component. This universal circuit structure can generate pulse signals with different widths and characteristics to accommodate various memory access requirements, making the circuit adaptable to different performance needs without requiring multiple separate circuits.
Solution Approach 2:
The invention segments the pulse generation function into two independent components: a clock frequency division component and a time delay component. This segmentation allows each component to be optimized independently while maintaining overall simplicity, and enables flexible configuration to meet different access performance requirements without increasing overall circuit complexity significantly.
Data Source
AI summary
A pulse signal generation circuit includes a clock frequency division component, a time delay component and a selection component. The clock frequency division component is configured to perform frequency division on a clock signal to generate a clock frequency division signal; the time delay component is configured to generate a time delay signal based on the clock frequency division signal; and the selection component is configured to receive the clock frequency division signal and the time delay signal at the same time, and select the clock frequency division signal and the time delay signal according to a preset condition to generate a pulse signal.