Split Multiplier Arrays With Independent Clocks for Lower Power
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Solution Overview
Problem
Data processing apparatuses face challenges in reducing power consumption due to the processor-intensive nature of multiplication operations, which often result in large and power-hungry circuits.
Innovation Solution
The implementation of separate A×B and C×D multiplier arrays, each clocked by distinct clock signals, allows for efficient operation and power-saving by 'freezing' one array at a time, eliminating the need for additional logic gates and reducing energy consumption without increasing circuit space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single large multiplier array is used to handle all multiplication operations, then the data processing apparatus can perform complete multiplication operations, but the circuit size and power consumption increase significantly
Solution Approach 1:
The patent divides a single large multiplier array into multiple smaller multiplier arrays (e.g., first multiplier array and second multiplier array). Each smaller array handles a portion of the multiplication operation, producing partial products that are later combined. This segmentation reduces the power consumption and circuit size of each individual array while maintaining the overall multiplication capability through parallel operation and combination of results.
2Use of energy by moving object
If multiple multiplier arrays are provided to reduce power consumption by selective activation, then power efficiency improves, but the circuit space and device complexity increase
Solution Approach 1:
The patent designs multiple multiplier arrays that can function both independently and in combination. The smaller multiplier arrays can be selectively activated based on the specific multiplication operation required, allowing the system to adapt its resource usage. This multi-functionality enables the same hardware resources to serve different operation sizes, improving power efficiency without proportionally increasing circuit space.
3Ease of operation
If separate clock signals are used for each multiplier array to enable selective activation, then power-saving control improves, but the device complexity increases
Solution Approach 1:
The patent employs dynamic clock signal control where each multiplier array has its own independently controllable clock signal. This allows the system to dynamically enable or disable specific multiplier arrays based on the operational requirements, achieving fine-grained power management. The dynamic control mechanism provides flexibility in activating only the necessary arrays for each multiplication task, balancing ease of operation with controlled device complexity.
Data Source
AI summary
A data processing apparatus is provided. An A×B multiplier array has a group of logic gates clocked by a first clock signal, where A and B are both integers. A C×D multiplier array, separate from the A×B multiplier array, has second group of logic gates clocked by a second clock signal, where C and D are both integers. Addition circuitry performs an addition operation between a first at least partial product produced by the A×B multiplier array and a second at least partial product produced by the C×D multiplier array.