Glitch-Free Clock Multiplexer Without a Reference Clock
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Solution Overview
Problem
Existing glitch-free clock multiplexers require a reference clock at all times, are sensitive to noisy environments and delays in the data path, leading to undefined or no clock selection, which affects the functionality of downstream IP blocks.
Innovation Solution
The proposed solution activates clock paths for each clock upon startup, deactivating unselected clocks and activating only the selected clock, eliminating the need for a reference clock and making the system insensitive to noise and delays by ensuring clock interchangeability at any time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reference clock is used to control clock multiplexing, then clock selection can be made, but the system becomes sensitive to noise and delays, leading to undefined clock selection
Solution Approach 1:
The patent removes the reference clock from the clock multiplexing control mechanism. Instead of using a separate reference clock to control the multiplexer, the system uses the clock signals themselves directly, eliminating the harmful sensitivity to noise and delays that the reference clock introduced.
Solution Approach 2:
The patent introduces a new control mechanism that acts as an intermediary between clock sources and the multiplexer. This mechanism uses enable signals and AND gates to control clock passage without requiring a reference clock, thereby mediating the clock selection process in a noise-immune manner.
2Ease of operation
If a reference clock is required at all times, then clock multiplexing can be controlled, but power consumption increases and real-estate requirements increase
Solution Approach 1:
The patent implements periodic enabling of clock paths based on selection signals rather than continuous operation. Clock paths are enabled only when needed for the selected clock source, and disabled otherwise, creating a periodic action pattern that reduces power consumption compared to keeping the reference clock active at all times.
Solution Approach 2:
The patent discards the continuous operation requirement of the reference clock and recovers functionality through selective enabling of clock paths. By disabling unused clock paths and recovering only the necessary clock signal when selected, the system reduces power consumption while maintaining operational capability.
3Adaptability or versatility
If multiple clock paths are kept active, then clock switching can be performed, but the physical real-estate requirements in the clock tree increase
Solution Approach 1:
The patent segments the clock distribution tree into multiple independently controllable paths, each with its own enable signal. This segmentation allows individual clock paths to be activated or deactivated based on selection, reducing the need for all paths to be permanently active and thereby reducing overall real-estate requirements while maintaining switching capability.
4Speed
If clock paths are activated without deactivating unselected clocks first, then switching is faster, but noise and delays cause undefined clock selection
Solution Approach 1:
The patent applies preliminary action by deactivating unselected clock paths before activating the selected clock path. The enable signals are controlled to ensure that clock paths are turned off first, then the selected path is turned on, preventing any period where multiple undefined clock signals could simultaneously affect the output.
Data Source
AI summary
Systems and methods disclosed herein provide for an improved glitch-free clock multiplexer exhibiting noise insensitivity with reduced power consumption and reduced physical area on a chip. The embodiments disclosed herein operate without any need of a reference clock. Due to which, clock interchangeability is possible at any point of time. An example glitch-free clock multiplexing according to the embodiments disclosed herein utilize a plurality of clock path circuits, each corresponding to a clock. The clock path circuits are activated responsive to a system startup signal. Based on a clock selection, the embodiments herein deactivate clock path circuits for unselected clocks and, dependent on the deactivation of the unselected clock path circuits, activate clock path circuits of any selected clocks.