Segmented Clock Counter for High-Frequency Carry Delay Limits
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Solution Overview
Problem
High-frequency clock counters above 1 GHz experience operating frequency limitations and counting errors due to carry operation delay times exceeding the count clock period, affecting the performance and reliability of functional circuits in control chips.
Innovation Solution
A clock counter design incorporating a clock frequency-dividing circuit, multiple counting circuits, and an adding circuit that divides the clock signal into frequency-divided signals, allowing each counting circuit to count pulses independently and summing initial count values to generate a target count value, thereby reducing carry operation delay and preventing counting errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high-frequency clock counter operating above 1 GHz is designed, then the operating speed of control chips is improved, but carry operation delay time exceeds the count clock period causing counting errors
Solution Approach 1:
The patent divides the clock signal frequency into multiple lower frequency-divided clock signals using a clock frequency-dividing circuit. Each counting circuit then counts pulses of these divided signals separately, and the adding circuit sums the initial count values to produce the final target count value. This segmentation approach reduces the carry operation delay time for each counting circuit while maintaining accurate overall counting, thereby resolving the contradiction between high operating speed and counting accuracy.
2Productivity
If the operating frequency of the clock counter is increased above 1 GHz, then the performance of functional circuits is improved, but carry operation delay causes counting errors
Solution Approach 1:
The patent segments the high-frequency clock signal into multiple lower-frequency divided signals through the clock frequency-dividing circuit. Each counting circuit processes these divided signals independently with reduced delay, and the adding circuit combines the results. This enables the system to operate at high frequencies while maintaining reliability by ensuring carry operation delay remains within acceptable limits for each segmented counting operation.
3Device complexity
If a single counting circuit is used for high-frequency clock signals, then the device complexity is reduced, but counting errors occur due to excessive carry operation delay
Solution Approach 1:
The patent introduces multiple counting circuits that each process frequency-divided clock signals separately. Although this increases the number of components, each counting circuit operates at a lower frequency with manageable delay characteristics. The adding circuit then combines their outputs to achieve accurate high-frequency counting, trading moderate complexity increase for significant reliability improvement.
Solution Approach 2:
The clock frequency-dividing circuit acts as an intermediary that transforms the high-frequency clock signal into multiple lower-frequency divided signals before they reach the counting circuits. This intermediary step reduces the operational burden on each counting circuit, preventing carry operation delay from exceeding the clock period, and thereby ensuring counting accuracy without requiring an overly complex single-circuit design.
Data Source
AI summary
Embodiments relate to a clock counter, a method for clock counting, and a storage apparatus. The clock counter includes a clock frequency-dividing circuit, a plurality of counting circuits, and an adding circuit. The clock frequency-dividing circuit receives a clock signal and divide a frequency of the clock signal to output a plurality of frequency-divided clock signals, sum of number of pulses of the plurality of frequency-divided clock signals being equal to number of pulses of the clock signal. The plurality of counting circuits are connected to the clock frequency-dividing circuit, each of the plurality of counting circuits being configured to respectively count pulses for each of the plurality of frequency-divided clock signals and generate an initial count value. The adding circuit is connected to the plurality of counting circuits, and adds up the initial count values of the plurality of counting circuits to generate a target count value.