Clock Generation Circuit for Staggered Latch Timing
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Solution Overview
Problem
Existing latches in large-scale data computing devices face issues with data collusion due to cascaded connections, leading to increased buffer usage, power consumption, and reduced accuracy in data transmission and latching.
Innovation Solution
A clock generation circuit with an input drive circuit, latch circuit, edge shaping circuit, feedback delay circuit, and output drive circuit is designed to generate phase-inverted clock signals, reducing buffer usage and ensuring complete staggering of clock signal phases, thereby improving data transmission accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If cascaded latches are used for data transmission, then data transmission capability is improved, but data collusion occurs and transmission accuracy deteriorates
Solution Approach 1:
A clock generation circuit is introduced as an intermediary component between the clock source and cascaded latches. This circuit generates multiple phase-shifted clock signals that are distributed to different latch stages, preventing data collusion by ensuring proper timing separation between cascaded latches while maintaining data transmission capability
2Adaptability or versatility
If clock buffers are added to drive cascaded latches, then clock signal distribution capability is improved, but device complexity and buffer quantity increase
Solution Approach 1:
The clock generation circuit performs multiple functions: it generates clock signals, provides phase shifting, and distributes clocks to multiple latch stages simultaneously. This multi-functional design replaces what would otherwise require separate buffer components, reducing overall device complexity while maintaining distribution capability
3Length of stationary object
If more clock buffers are used to drive cascaded latches, then clock signal reach is improved, but power consumption increases
Solution Approach 1:
The clock generation circuit uses periodic phase-shifting to distribute clock signals to different latch stages at different time intervals. This periodic action ensures that clock signals reach distant latches without requiring continuous high-power buffering, as each latch receives its clock signal in a staggered, energy-efficient manner
Data Source
AI summary
A clock generation circuit, a latch using same, and a computing device are provided. The clock generation circuit includes an input end, configured to input a pulse signal; a first output end, configured to output a first clock signal; a second output end, configured to output a second clock signal; and an input drive circuit, a latch circuit, an edge shaping circuit, a feedback delay circuit, and an output drive circuit, where the input drive circuit, the latch circuit, the edge shaping circuit, the feedback delay circuit, and the output drive circuit are sequentially connected between the input end and the first output end as well as the second output end in series. A clock pulse can be effectively shaped, the use of a clock buffer can be reduced, and the correctness and accuracy of data transmission and latching can be improved.