Clock Gating Debug Unit for Accurate FPGA Verification
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Solution Overview
Problem
The clock gating function in chip design cannot be accurately verified during FPGA testing due to limited clock resources, which exceeds the clock gate quantity requirements, making it difficult to assess the effectiveness of clock gating in chip circuits.
Innovation Solution
A debugging unit is introduced, comprising a register and a clock control unit that generates a control signal based on a clock enable signal to control the clock signal, allowing the register to sample input data only during the validity period, enabling effective testing of the clock gating function in FPGA tests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If clock gating function is used to disable clock of logic unit, then switching power consumption is reduced, but accuracy of clock gating function cannot be verified in FPGA test due to limited clock resources
Solution Approach 1:
The patent segments the clock control function by introducing a debugging unit with a clock control unit that can independently control clock signals for different clock gates. This segmentation allows each clock gate to have its own dedicated clock control, enabling accurate verification of clock gating function without requiring proportional increase in FPGA clock resources. The clock control unit generates control signals based on clock enable signals to selectively control clock distribution to registers.
Solution Approach 2:
The patent introduces a debugging unit as an intermediary component between the existing clock resources and the clock gates that need verification. This debugging unit includes a clock control unit that acts as a mediator to generate and distribute controlled clock signals to multiple clock gates, enabling accurate verification of clock gating function while using limited FPGA clock resources.
2Device complexity
If one clock is used in one clock region with maximum 24 clock regions, then FPGA clock resource limitation is accepted, but clock gate quantity requirement cannot be satisfied
Solution Approach 1:
The patent implements multi-functionality by designing a debugging unit where a single clock control unit can control multiple clock gates. The clock control unit receives clock enable signals and generates control signals to distribute clock signals to multiple registers, allowing one FPGA clock region to serve multiple clock gating functions that would otherwise require separate clock regions.
Solution Approach 2:
The patent merges multiple clock control functions into a single debugging unit. The clock control unit combines the functionality of controlling multiple clock gates into one integrated component, allowing multiple clock enable signals to be processed and distributed through a unified control mechanism, thereby reducing the number of required clock regions.
3Measurement precision
If each clock gate is provided with independently controlled clock, then clock gating function can be verified accurately, but FPGA clock resources are insufficient
Solution Approach 1:
The patent transitions from a spatial dimension solution (providing separate physical clock regions for each clock gate) to a temporal/control dimension solution (using a debugging unit with clock control unit that dynamically controls clock distribution). This dimensional change allows accurate verification of clock gating function without requiring proportional increase in physical clock resources.
Data Source
AI summary
The present invention discloses a debugging unit and a processor. The debugging unit includes; a register, adapted to sample input data under control of a clock signal; and a dock control unit, adapted to generate a control signal based on a clock enable signal to control the clock signal, so that the register is controlled to sample the input data in a validity period of the clock signal when the control signal is valid. The present invention also discloses a corresponding system-on-chip and an intelligent device including the system-on-chip.