Regenerative Sampler Circuit for Fast Small-Signal Bit Capture
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Solution Overview
Problem
High-speed samplers in high-speed serializer/deserializer applications face challenges in capturing data bits from small signals at high data rates due to limited sensitivity and speed limitations in existing regeneration circuits.
Innovation Solution
The regeneration circuit design includes a configuration of inverting circuits, transistors, and switches that enable regenerative feedback during the regeneration phase, with pull-up and pull-down circuits to enhance signal strength and speed, allowing for faster conversion of input voltages into differential output voltages, thereby improving bit resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the regeneration circuit uses conventional configuration, then the circuit complexity is low, but the speed and sensitivity of bit capture are limited
Solution Approach 1:
The regeneration circuit is segmented into multiple inverting circuits (first, second, third, and fourth inverting circuits) with distinct functions. Each inverting circuit processes signals independently, allowing parallel operation that increases bit capture speed while distributing the overall circuit complexity across modular units.
Solution Approach 2:
The patent introduces a differential signal processing dimension by using paired inverting circuits with complementary inputs and outputs. This differential architecture enables simultaneous processing of multiple signal paths, increasing speed without proportionally increasing complexity through efficient signal representation.
2Measurement precision
If the regeneration circuit uses conventional configuration, then the manufacturing is simple, but the sensitivity to capture data bits from small signals is limited
Solution Approach 1:
The regeneration circuit implements regenerative feedback by coupling the output of the first inverting circuit to the input of the second inverting circuit, and the output of the second inverting circuit to the input of the first inverting circuit. This feedback mechanism amplifies small input signals through multiple passes, significantly improving sensitivity to weak signals while maintaining manageable circuit complexity through the systematic feedback loop design.
Solution Approach 2:
The patent merges multiple inverting circuits into a unified regeneration system where the circuits work cooperatively. The first and second inverting circuits process differential signals together, and the third and fourth inverting circuits provide additional signal paths, combining their effects to achieve high sensitivity without requiring each individual circuit to be overly complex.
3Power
If the regeneration circuit uses conventional configuration, then the device structure is simple, but the ability to generate large differential output voltage quickly is limited
Solution Approach 1:
The circuit performs preliminary signal conditioning in the first and second inverting circuits before the final differential output is generated. The input signals are pre-processed and amplified through the feedback loops, so that when the differential output is produced, it already has sufficient voltage level and speed, achieving high power output without requiring a single overly complex amplification stage.
Data Source
AI summary
A regeneration circuit includes a first inverting circuit and a second inverting circuit. The regeneration circuit also includes a first transistor coupled to an input of the second inverting circuit, and a second transistor coupled to an input of the first inverting circuit, a third transistor and a fourth transistor. A gate of the first transistor and a gate of the fourth transistor are coupled to a first input, and a gate of the second transistor and a gate of the fourth transistor are coupled to a second input. The regeneration circuit further includes a first switch and a second switch. The first switch and the third transistor are coupled in series between a first rail and the first transistor, and the second switch and the fourth transistor are coupled in series between the first rail and the second transistor.