Dual-Adder Circuit for Non-Power-of-Two Width Addition
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Solution Overview
Problem
Tree adders experience additional delay when handling input widths that cross a power of two boundary due to the introduction of an extra level of gate delay in group propagate-generate logic, affecting the efficiency of addition operations.
Innovation Solution
The proposed solution involves a dual-adder circuit architecture where a first adder circuit computes the sum of a power of two bits, and a second carry select adder circuit computes both incremented and non-incremented sums of the remaining bits, with the carry out bit from the first adder used to select one of the possible outputs from the second adder, allowing for concurrent computation and concatenation of sums without additional delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If tree adder is used for power of two input widths, then addition speed is improved, but device complexity increases when handling non-power of two widths due to extra gate delay levels
Solution Approach 1:
The adder is divided into two separate adder circuits: a first adder circuit that handles the most significant bits (power of two width) and a second adder circuit that handles the least significant bits (remaining bits). This segmentation allows each circuit to be optimized independently, with the first circuit using tree adder logic for high-speed MSB computation and the second circuit handling LSB computation with carry select logic, thereby avoiding the need for a single complex adder that would require additional gate delay levels to handle non-power-of-two widths.
2Device complexity
If conventional single adder circuit is used for non-power of two widths, then device complexity is reduced, but addition speed decreases due to extra delay levels
Solution Approach 1:
The first adder circuit computes the most significant bits of the sum in advance using optimized tree adder logic, generating a preliminary carry out bit. This preliminary computation allows the second adder circuit to start its computation earlier with the benefit of the already-computed MSBs, effectively overlapping the computation stages and reducing the total addition time despite the non-power-of-two width.
Solution Approach 2:
The solution transitions from a single-dimensional adder design to a two-dimensional approach by separating the addition into MSB and LSB portions that are computed in parallel by different circuits. The final sum is constructed by concatenating the MSB sum from the first adder circuit with the LSB sum from the second adder circuit, effectively adding a dimensional separation that avoids the sequential delay inherent in conventional single adder designs for non-power-of-two widths.
Data Source
AI summary
A method includes receiving, by an x-bit adder, first and second addends. The x bits comprise a first portion and a second portion, the first portion is a power of two number of bits, and x is not a power of two. The method also includes computing a first sum of the first and second addends corresponding to the first portion. Computing the first sum provides a carry out bit. The method includes computing a non-incremented sum of the first and second addends corresponding to the second portion; computing an incremented sum of the first and second addends corresponding to the second portion; selecting one of the non-incremented sum and the incremented sum, responsive to the carry out bit, as a second sum; and providing a final sum by concatenating the second sum and the first sum.