Primary Pulse Duty Correction for Memory Strobe Recognition
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Solution Overview
Problem
Memory devices face challenges in correcting duty ratio distortions of primary pulses due to signal interference during the preamble period of control signals, which can lead to delayed recognition of data strobe signals and potential re-reads.
Innovation Solution
A memory device and system that include a primary pulse correction module with a reset signal generation circuit, a primary pulse detection circuit, and a corrected primary pulse output circuit, which detect the end of the preamble period and adjust the rising edge of the pulse to correct the duty ratio, ensuring timely recognition of signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory device operates without duty ratio correction, then the device complexity is reduced, but the reliability deteriorates due to delayed recognition of data strobe signals and potential re-reads
Solution Approach 1:
The control signal processing is segmented into distinct functional modules: a reset signal generation circuit that generates reset signals based on control signals, a primary pulse detection circuit that detects primary pulses using the reset signals, and a corrected primary pulse output circuit that outputs corrected pulses. This segmentation allows each module to perform its specific function independently, improving reliability without requiring complete system redesign.
Solution Approach 2:
The system performs preliminary detection of the primary pulse during the preamble period before actual data transmission begins. The primary pulse detection circuit identifies the first pulse after the preamble, and the corrected primary pulse output circuit prepares corrected pulses in advance. This preliminary action ensures that duty ratio corrections are applied before critical data strobe signal recognition occurs, preventing delays and re-reads.
2Productivity
If the memory device corrects duty ratio of primary pulses, then the productivity is improved by preventing re-reads, but the device complexity increases due to additional correction circuits
Solution Approach 1:
The duty ratio correction is applied locally only to the primary pulse (the first pulse after the preamble period) rather than to all control signals uniformly. The corrected primary pulse output circuit specifically targets and corrects only the initial pulse that sets the timing reference for subsequent data strobe signals. This localized correction approach improves productivity by preventing re-reads caused by timing errors while minimizing the complexity increase to only what is necessary for primary pulse correction.
Solution Approach 2:
The system generates a corrected version of the primary pulse by creating a copy with adjusted timing characteristics. The corrected primary pulse output circuit produces a corrected pulse that replicates the function of the original primary pulse but with corrected duty ratio. This copying approach allows the system to maintain the original control signal structure while introducing a corrected variant that improves signal recognition accuracy and prevents re-reads.
3Loss of time
If the memory device detects and corrects primary pulse duty ratio, then the loss of time is reduced by avoiding re-reads, but the measurement precision requirements increase for detecting pulse edges
Solution Approach 1:
The reset signal generation circuit acts as an intermediary between the control signal input and the primary pulse detection. It generates reset signals that synchronize and standardize the timing reference for pulse detection. This intermediary component simplifies the measurement task by providing a clean, standardized timing baseline, thereby reducing the precision burden on the primary pulse detection circuit while still enabling accurate duty ratio correction to prevent time loss from re-reads.
Data Source
AI summary
The present disclosure relates to a memory device for correcting a pulse duty ratio and a memory system including the same, and relates to a memory device which corrects the duty ratio of a primary pulse of a memory device control signal, and a memory system including the same.