Parallel DRAM ECC Decoding for Faster Error Correction
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Solution Overview
Problem
As semiconductor memory technologies advance and memory density increases, errors in Dynamic Random Access Memory (DRAM) become more prevalent, affecting performance, and existing Error Checking and Correction (ECC) techniques face challenges in efficiently detecting and correcting errors during read and write operations.
Innovation Solution
An error correction system is designed for DRAM that generates X first operation codes and Y second operation codes, utilizing M decoding units with decoders, AND gate units, and NOR gate units to detect and correct errors by dividing data into M bytes with N bits, allowing for simultaneous error detection and correction across all bytes, optimizing hardware usage and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ECC techniques are used for error detection and correction in high-density DRAM, then error correction capability is maintained, but hardware complexity and power consumption increase
Solution Approach 1:
The patent divides the data into M bytes with N bits each, and divides the error correction codes into two types: first operation codes (X codes) for bit-level error correction within each byte, and second operation codes (Y codes) for byte-level error correction across multiple bytes. This segmentation allows parallel processing and reduces the complexity of any single decoding unit while maintaining overall error correction capability.
Solution Approach 2:
The patent introduces a two-dimensional error correction approach by creating separate code dimensions: first operation codes operating on the bit dimension within bytes, and second operation codes operating on the byte dimension across the data array. This dimensional separation enables efficient error correction without requiring a single complex decoding mechanism.
2Reliability
If traditional ECC techniques are used for error detection and correction in high-density DRAM, then error correction capability is maintained, but power consumption increases
Solution Approach 1:
The patent segments the error correction process into multiple independent decoding units, each handling a specific byte and its associated first operation codes. This segmentation enables selective activation of decoding units based on error patterns, reducing overall power consumption compared to always activating a single complex ECC decoder.
Solution Approach 2:
The patent uses first operation codes to correct errors at the bit level within individual bytes, which is a partial correction approach. This allows the system to handle common single-bit errors efficiently without requiring full byte-level reclamation, thereby reducing power consumption while maintaining adequate error correction capability for typical error patterns.
3Reliability
If traditional ECC techniques are used for error detection and correction, then error correction is performed sequentially, but error correction speed decreases
Solution Approach 1:
The patent divides the data into M independent bytes, each with its own decoding unit that can operate in parallel on first operation codes. This segmentation enables simultaneous error correction across multiple bytes, dramatically increasing error correction speed compared to sequential processing of a single large data block.
Solution Approach 2:
The patent combines parallel bit-level correction (using first operation codes on individual bytes) with byte-level correction (using second operation codes across bytes) into a unified error correction system. This merging of parallel operations with coordinated byte-level management achieves high-speed error correction while maintaining comprehensive error handling capability.
4Reliability
If more operation codes are used for comprehensive error correction, then error correction capability improves, but hardware complexity increases
Solution Approach 1:
The patent segments the operation codes into two distinct types with different functions: first operation codes (X codes) for efficient bit-level correction within bytes, and second operation codes (Y codes) for byte-level correction across the data array. This segmentation organizes the large number of codes into manageable groups, reducing the perceived complexity while maintaining comprehensive error correction capability.
Solution Approach 2:
The patent creates a universal error correction framework where first operation codes can correct errors in any byte independently, and second operation codes provide backup and cross-byte error correction. This multi-functional code system handles various error patterns (single-bit, multi-bit, cross-byte errors) using a unified approach, reducing complexity compared to having separate specialized codes for each error type.
Data Source
AI summary
An error correction system includes M decoding units, each configured to perform decoding on the X first operation codes and the Y second operation codes; the decoding unit includes: a decoder, configured to receive the X first operation codes and output N first decoded signals, each corresponding to a respective one bit of the N data; a first AND gate unit, configured to receive and perform a logical AND operation on Z selected operation codes; an NOR gate unit, configured to receive and perform a logical NOR operation on (Y−Z) unselected operation codes; and N second AND gate units, each having an input terminal connected to an output terminal of the first AND gate unit, an output terminal of the NOR gate unit and one of the first decoded signals.