Memory Readout Circuit Sharing for DBI and Built-In Self-Test
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Solution Overview
Problem
Conventional memory devices require redundant circuits for both data bus inversion and built-in self-test functions, leading to increased power consumption and circuit layout area, which hampers data readout performance.
Innovation Solution
A memory device design that incorporates a data bus inversion calculator, multiplexer, and output result judging circuit, allowing for shared circuitry to handle both normal and test modes without redundant judging circuits, thereby reducing the load on the data read-out path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant judging circuits are configured for built-in self-test function, then error detection capability is improved, but device complexity and circuit layout area increase
Solution Approach 1:
The output result judging circuit is designed to perform multiple functions: in normal operation mode it judges data bus inversion results, and in test mode it judges built-in self-test results. This multi-functional design eliminates the need for separate redundant judging circuits, reducing device complexity while maintaining error detection capability.
Solution Approach 2:
The patent merges the normal operation judging function and the built-in self-test judging function into a single output result judging circuit. By combining these functions and using a mode signal to switch between them, the circuit layout area and device complexity are reduced while preserving both error detection capabilities.
2Reliability
If redundant judging circuits are configured for built-in self-test function, then error detection capability is improved, but power consumption increases
Solution Approach 1:
The output result judging circuit serves dual purposes by processing both normal operation data and test data through the same hardware circuit. This eliminates the need for parallel redundant circuits that would consume additional power, while maintaining full error detection capability for both operation modes.
Solution Approach 2:
By merging the judging functions for normal operation and built-in self-test into a single circuit, the patent reduces the total number of active circuits required. This consolidation directly reduces power consumption since fewer circuit components are needed, while the circuit maintains the ability to detect errors in both operational contexts.
3Reliability
If redundant judging circuits are configured for built-in self-test function, then error detection capability is improved, but data readout performance deteriorates
Solution Approach 1:
The single output result judging circuit handles both normal data readout judgment and test result judgment without requiring separate dedicated circuits. This universal approach reduces the circuit load on the data readout path, improving data readout performance while maintaining error detection capability through the same circuit in different operational modes.
Data Source
AI summary
A memory device includes a memory cell array, a data accessing circuit, a data bus inversion calculator, a multiplexer, and an output result judging circuit. The data accessing circuit performs a data write-in operation or a data read-out operation on the memory cell array. The data accessing circuit reads read-out data from the memory cell array. The data bus inversion calculator generates inversion indication data according to the read-out data. The multiplexer outputs the inversion indication data or test data according to a mode signal. The output result judging circuit compares the read-out data with the inversion indication data or the test data to generate output information.