Pseudo-Triple-Port SRAM Bitcell Layout for Dense Dual-Port Access
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Solution Overview
Problem
Conventional dual-port SRAMs face challenges in achieving high density due to the need for extra access transistors, which compromises their density and efficiency in supporting simultaneous multiple read or write operations.
Innovation Solution
The implementation of a pseudo-triple-port SRAM design, where each bitcell has two independent word lines for access transistors, allowing for single-ended read operations and differential write operations using a pair of bit lines, thereby increasing density and enabling simultaneous read/write operations without the need for additional transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dual-port SRAM is used to enable simultaneous multiple read or write operations, then operational capability is improved, but device complexity increases due to extra access transistors
Solution Approach 1:
Each bitcell is designed with two access transistors that can serve multiple functions: they enable both single-ended read operations through individual bit lines and differential write operations through the same bit lines. This multi-functionality allows the bitcell to support dual-port operations without requiring separate access transistor pairs for each port, thereby reducing overall device complexity while maintaining operational capability.
Solution Approach 2:
The patent merges the read and write access transistors into a single shared pair of access transistors per bitcell. Instead of having separate access transistor pairs for read and write operations, the same transistors are used for both operations by controlling them through different word line signals, reducing the total transistor count while enabling simultaneous read/write operations.
2Adaptability or versatility
If extra access transistors are added for dual-port operation, then operational capability is improved, but memory density decreases
Solution Approach 1:
The access transistors are designed to serve dual purposes: they enable both read operations when activated by read word lines and write operations when activated by write word lines. This multi-functionality eliminates the need for additional dedicated write access transistors, maintaining memory density while achieving dual-port operation capability.
Solution Approach 2:
The patent combines the read and write access functions into a single pair of access transistors per bitcell. By sharing the same physical transistors for both read and write operations through different control mechanisms, the design achieves dual-port functionality without increasing the transistor count, thereby preserving memory density.
3Device complexity
If conventional SRAM architecture is used, then simplicity is maintained, but operational capability for simultaneous operations is limited
Solution Approach 1:
The patent introduces dynamic control mechanisms where word line controllers can independently assert different word lines (read word lines and write word lines) to dynamically switch between read and write operations. This dynamic control allows the same physical architecture to adapt to different operational modes, enabling simultaneous read/write operations while maintaining architectural simplicity.
Solution Approach 2:
The word line control is segmented into separate read word lines and write word lines, allowing independent control of read and write operations. This segmentation enables the memory to perform simultaneous read and write operations by activating different word line pairs, enhancing operational capability while keeping the bitcell structure simple and unified.
Data Source
AI summary
A pseudo-triple-port memory is provided with read datapaths and write datapaths. The pseudo-triple-port memory includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port coupled to a first bit line, a second read port coupled to a second bit line, and a write port coupled to the first bit line and to the second bit line.