Complementary Clock Gate for Low-Power Flip-Flop Switching

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Solution Overview

Problem

Conventional C2MOS flip-flop circuits experience high dynamic power consumption and large area due to redundant clock switching, which limits their operation at low voltages and energy efficiency, and are susceptible to process variations.

Innovation Solution

A complementary clock gate and low-power flip-flop circuit design that minimizes redundant clock switching by merging topologically equivalent transistors, using a NOR gate and NAND gates with specific transistor configurations to reduce unnecessary transistors and enhance energy efficiency, allowing operation at low voltages while maintaining tolerance to process variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If conventional C2MOS flip-flop circuit is used with multiple transistors for clock switching, then the circuit can perform basic flip-flop function, but the dynamic power consumption increases and area increases due to redundant clock switching

Engineering Contradiction:
Improvedynamic power consumptionVSAvoidnumber of transistors
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent merges topologically equivalent transistors (specifically PMOS transistors p1 and p2, and NMOS transistors n1 and n2) that perform identical clock switching functions. By combining these redundant transistors into single equivalent transistors, the circuit eliminates unnecessary components while maintaining the flip-flop's core functionality, thereby reducing dynamic power consumption and area without sacrificing operational capability

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent extracts and removes redundant clock switching transistors from the conventional C2MOS flip-flop circuit. By identifying and eliminating the duplicate PMOS and NMOS transistors that perform redundant clock switching operations, the design reduces the overall transistor count and associated power consumption while preserving the essential flip-flop operation

Inventive Principle:
Principle #2Taking out (Extraction)

2Area of stationary object

If conventional C2MOS flip-flop circuit is used, then the circuit structure is simple, but the area increases due to redundant transistors and clock switching components

Engineering Contradiction:
Improvecircuit areaVSAvoidnumber of transistors
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent merges topologically equivalent transistors (specifically PMOS transistors p1 and p2, and NMOS transistors n1 and n2) that perform identical clock switching functions. By combining these redundant transistors into single equivalent transistors, the circuit eliminates unnecessary components while maintaining the flip-flop's core functionality, thereby reducing dynamic power consumption and area without sacrificing operational capability

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent extracts and removes redundant clock switching transistors from the conventional C2MOS flip-flop circuit. By identifying and eliminating the duplicate PMOS and NMOS transistors that perform redundant clock switching operations, the design reduces the overall transistor count and associated power consumption while preserving the essential flip-flop operation

Inventive Principle:
Principle #2Taking out (Extraction)

3Temperature

If conventional C2MOS flip-flop circuit is used, then the circuit can operate at standard voltages, but it cannot operate efficiently at low voltages due to high power consumption

Engineering Contradiction:
Improveoperating voltageVSAvoidpower consumption
Core Design Contradiction:
TemperatureVSUse of energy by moving object

Solution Approach 1:

The patent merges topologically equivalent transistors (specifically PMOS transistors p1 and p2, and NMOS transistors n1 and n2) that perform identical clock switching functions. By combining these redundant transistors into single equivalent transistors, the circuit eliminates unnecessary components while maintaining the flip-flop's core functionality, thereby reducing dynamic power consumption and area without sacrificing operational capability

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent extracts and removes redundant clock switching transistors from the conventional C2MOS flip-flop circuit. By identifying and eliminating the duplicate PMOS and NMOS transistors that perform redundant clock switching operations, the design reduces the overall transistor count and associated power consumption while preserving the essential flip-flop operation

Inventive Principle:
Principle #2Taking out (Extraction)

4Reliability

If redundant clock switching transistors are used in C2MOS flip-flop, then the circuit maintains process variation tolerance, but the area and power consumption increase

Engineering Contradiction:
Improveprocess variation toleranceVSAvoidcircuit area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges topologically equivalent transistors (specifically PMOS transistors p1 and p2, and NMOS transistors n1 and n2) that perform identical clock switching functions. By combining these redundant transistors into single equivalent transistors, the circuit eliminates unnecessary components while maintaining the flip-flop's core functionality, thereby reducing dynamic power consumption and area without sacrificing operational capability

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent extracts and removes redundant clock switching transistors from the conventional C2MOS flip-flop circuit. By identifying and eliminating the duplicate PMOS and NMOS transistors that perform redundant clock switching operations, the design reduces the overall transistor count and associated power consumption while preserving the essential flip-flop operation

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS11621706B2Complementary clock gate and low power flip-flop circuit including same
Publication Date: 2023.04.04 RES & BUSINESS FOUND SUNGKYUNKWAN UNIV
  • US11621706B2 patent drawing
  • US11621706B2 patent drawing
  • US11621706B2 patent drawing

AI summary

A complementary clock gate, includes a NOR gate configured to receive a data signal D and a signal QI; a first P-type transistor gated by an output value of the NOR gate; and a NAND gate, connected in series to the first P-type transistor, configured to receive a clock signal CK and an inverted data signal DN, and output an inverted clock signal CKB.