Mux-D Scan Flip-Flop Topology Without Critical-Path Mux Delay
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Solution Overview
Problem
Traditional Mux-D scan flip-flop designs suffer from delay overhead due to the presence of a scan multiplexer in the critical path, limiting frequency performance and requiring complex scan methodologies, while also consuming significant area and power.
Innovation Solution
The proposed fast Mux-D scan flip-flop bypasses the traditional input data scan multiplexer to the master keeper side path, removing delay overhead and allowing for a simpler scan methodology, smaller area, and reduced power consumption, while maintaining high performance comparable to level sensitive scan designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a traditional input data scan multiplexer is used in the critical path, then scan functionality is achieved, but delay overhead increases and frequency performance is limited
Solution Approach 1:
The patent extracts the scan multiplexer from the critical data path and relocates it to a non-critical path. The scan path is separated from the main data flow, allowing the critical path to operate without the delay overhead of the multiplexer while still maintaining scan functionality through the relocated scan path.
Solution Approach 2:
The patent segments the data path into separate scan and non-scan paths. By dividing the original unified path into distinct segments, the scan multiplexer operations are isolated from the critical data path, eliminating its delay impact on frequency performance while preserving scan functionality in the dedicated scan path.
2Reliability
If traditional Mux-D scan flip-flop design is used, then scan functionality is achieved, but area consumption increases significantly
Solution Approach 1:
The patent extracts the scan multiplexer from the critical path and relocates it to a non-critical path, which reduces the area occupied by scan logic in the critical region. This extraction allows the main data path to be more compact while the scan path components are positioned in areas that do not constrain the overall cell size.
3Reliability
If traditional Mux-D scan flip-flop design is used, then scan functionality is achieved, but power consumption increases
Solution Approach 1:
The patent extracts the scan multiplexer from the critical data path, reducing the switching activity and power consumption in the critical path. By relocating the scan path to a non-critical region, the multiplexer operations occur less frequently and with lower impact on overall power consumption.
4Reliability
If scan logic is added to latches or flip-flops, then testability is improved, but standard cell size increases by approximately 70%
Solution Approach 1:
The patent segments the flip-flop into separate scan and non-scan paths, allowing the scan logic to be added without significantly increasing the standard cell size. By dividing the functionality into distinct segments, the scan path components are positioned efficiently to minimize area overhead while maintaining testability.
Solution Approach 2:
The patent repositions the scan path in a different spatial dimension or layout arrangement, placing it in a non-critical area that does not constrain the standard cell size. This dimensional reorganization allows scan functionality to be added without the 70% area increase typically associated with traditional scan logic integration.
Data Source
AI summary
A fast Mux-D scan flip-flop is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.