Binary Multiply-Accumulate System Using Weight Copies
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Solution Overview
Problem
Deep neural networks (DNNs) face inefficiencies in performing binary multiply-accumulate operations due to the high cost and complexity of floating-point operations, particularly in convolution processes, which consume significant die area and power.
Innovation Solution
A method involving the use of multiple partial copies of weights, where each copy is XORed with corresponding input bits and aggregated in destination sub-locations, with the filter index determining the number of copies and shifts, allowing for efficient binary multiply-accumulate operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If floating point values are used for DNN operations, then computational precision is improved, but power consumption and die area increase significantly
Solution Approach 1:
The patent changes the numerical representation parameter from floating-point to binary format, and transforms the computational operation from multiplication to XOR logic operations. This parameter transformation enables DNN operations to be performed using simple binary logic gates instead of complex floating-point arithmetic units, dramatically reducing power consumption while maintaining sufficient precision for binary-weighted neural network operations
2Measurement precision
If floating point values are used for DNN operations, then computational precision is improved, but device complexity increases significantly
Solution Approach 1:
The patent substitutes complex mechanical/computational systems (floating-point arithmetic units with multiplication and addition capabilities) with simpler binary logic systems using XOR gates and bit-shifting operations. This replacement eliminates the need for complex floating-point hardware while achieving the same functional outcome through binary logic operations
Solution Approach 2:
The patent changes the computational parameter representation from floating-point format to binary format, and transforms the mathematical operations from multiplication-accumulation to XOR-based logic operations. This parameter transformation simplifies the device architecture by replacing complex arithmetic logic units with basic logic gates
3Adaptability or versatility
If traditional convolution operations are implemented, then DNN functionality is achieved, but die area consumption increases
Solution Approach 1:
The patent substitutes traditional convolution operations that require large arithmetic logic units with binary-based operations using XOR gates and bit-manipulation instructions. This substitution maintains full DNN functionality including convolution, pooling, and activation operations while reducing the die area required for the neural network accelerator
Data Source
AI summary
Data structure and microcontroller architecture performing binary multiply-accumulate operations using multiple partial copies of weights. Destination-register location, source-register location, and weight-register location are received. Using the weight-register location, a sub-set of the weight bits is copied a select number of times based on a filter index value that is received. Each copy of the sub-set of weights is executed in parallel. Using the source-register location, a sub-set of the input bits is selected based on the size of the sub-set of weights, wherein the sub-set of input bits is shifted one bit from a previous sub-set of input bits. XOR operation is performed on each corresponding bit in the copy of the sub-set of weights with each corresponding bit in the selected sub-set of input bits. In a corresponding destination sub-location, output of each XOR operation is aggregated with each other and with current value of the corresponding destination sub-location.