Register Arrangements TRIZ Cases
- GPU Register Renaming via Fixed and Shared Partitioning
Dynamic register renaming logic partitions the GPU register file into fixed and shared sets to reuse variables across hardware contexts.
- Processor Architecture with Immutable Memory for Race Condition Elimination
A processor architecture uses a control unit to direct concurrent core operations through input buffers and versioned memory units.
- Multi-port Register File with Pipelined Write and Asynchronous Read
Segmented pipelined registers buffer write data for immediate forwarding during asynchronous reads, reducing latency and area overhead.
- Load-Store Device Strided Address Generator Parallel Memory Access
A load-store device uses a strided address generator to perform parallel memory access operations.
- Banked Register File with Address Translation for Graphics Shading
Banked register files translate logical identifiers to physical addresses, eliminating access conflicts and latency in multi-threaded graphics processing.
- Systolic Array Fine-Grained Sparsity Computation
A systolic array processes sparse matrices by selecting input elements via metadata to minimize rows used.