RISC-V Vector Extension Core Interface for Accelerator Communication

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The existing communication between RISC-V Vector extension (RVV) cores and accelerators is inefficient, leading to high delays and limited collaboration due to the absence of a direct connection, with tightly coupled accelerators being inflexible and loosely coupled ones experiencing software-related delays.

Innovation Solution

A RISC-V Vector extension (RVV) core with a command queue and an interface unit that generates accelerator commands, enabling direct communication with accelerators and reducing delays by using a shared RVV register and a queue-based FIFO module for efficient data transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If tightly coupled accelerators are used, then communication speed between accelerator and RVV is improved, but flexibility is reduced

Engineering Contradiction:

Improvecommunication speedVSAvoidflexibility

Core Design Contradiction:

SpeedVSAdaptability or versatility

Solution Approach 1:

The patent implements a dynamic coupling mechanism where the interface unit can adaptively adjust the communication interface configuration between the accelerator and RVV core. The command queue and interface unit are designed to dynamically handle different command types and data transfer modes, allowing the system to switch between tight coupling for speed-critical operations and loose coupling for flexibility-required operations, thus resolving the contradiction between communication speed and flexibility.

Inventive Principle:

Principle #15Dynamics

2Adaptability or versatility

If loosely coupled accelerators are used, then flexibility is improved, but communication delay increases

Engineering Contradiction:

ImproveflexibilityVSAvoidcommunication delay

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent introduces a command queue and interface unit as intermediary components between the accelerator and the RVV core. This intermediary layer buffers and manages communication commands, allowing flexible configuration while maintaining efficient data transfer. The command queue acts as a mediator that decouples the timing constraints between accelerator and RVV, reducing communication delay while preserving flexibility through programmable command handling.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Loss of time

If direct connection between RVV core and accelerator is established, then communication delay is reduced, but device complexity increases

Engineering Contradiction:

Improvecommunication delayVSAvoiddevice complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The interface unit is designed with multi-functionality to handle various communication tasks including command generation, data transfer management, and protocol conversion. By consolidating these functions into a single universal interface unit rather than separate dedicated circuits for each function, the patent achieves direct communication with reduced delay while minimizing the increase in device complexity through functional integration.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20240394057A1RISC-v vector extention core, processor, and system on chip

Publication Date: 2024.11.28 ALIBABA INNOVATION PRIVATE LIMITED

AI summary

A reduced instruction set computer (RISC)-V vector extension (RVV) core communicated with one or more accelerators. The RVV core includes: a command queue configured to output commands; and an interface unit communicatively coupled to the command queue and having circuitry configured to generate an accelerator command to an accelerator of the one or more accelerators based on the output commands.