Microprocessor Decoding Combined Microcode to Reduce Latency
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Solution Overview
Problem
Microprocessors face inefficiencies due to repeated microcode reading delays when processing complex instructions, which increases hardware costs and reduces performance.
Innovation Solution
Combining multiple complex instructions into a single combined microcode and storing it in a microcode controller memory, allowing for microcode reading to occur only once, thereby reducing latency and improving processor efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple complex instructions are processed separately with individual microcode reading, then each instruction can be decoded independently, but the processor experiences repeated microcode reading delays reducing overall efficiency
Solution Approach 1:
The patent combines multiple complex instructions into a single compound instruction that shares common microcode. When the instruction decoder detects a sequence of complex instructions that can be merged, it consolidates them into one compound instruction with shared microcode entries. This merging eliminates repeated microcode reading operations, as the shared microcode is read once and reused across multiple instruction contexts, directly reducing time loss and improving processing efficiency.
Solution Approach 2:
The instruction decoder performs preliminary detection and merging of complex instructions before they reach the microcode execution stage. By identifying potential compound instructions in advance and preparing the merged microcode structure, the system avoids the need for separate microcode reading operations during execution. This preliminary action ensures that when microcode reading occurs, it happens only once for the entire sequence rather than repeatedly for each individual instruction.
2Reliability
If separate microcode is stored for each complex instruction in read-only memory, then each instruction has dedicated microcode for accurate execution, but the hardware cost and memory requirements increase
Solution Approach 1:
The patent merges microcode storage by creating shared microcode entries that serve multiple complex instructions. Instead of storing separate microcode for each complex instruction, the system stores consolidated microcode in the read-only memory that can be accessed by multiple instructions. This merging reduces the total memory capacity required and simplifies the microcode memory structure while maintaining execution accuracy through the shared microcode design.
Solution Approach 2:
The patent implements universal microcode entries that can serve multiple functions and multiple complex instructions. A single microcode entry in the read-only memory is designed to handle various complex instructions that share common operational sequences. This multi-functionality approach reduces the overall complexity of the microcode storage system by eliminating redundant microcode copies while ensuring that each complex instruction can be executed accurately using the appropriate shared microcode.
Data Source
AI summary
Microcode combination of complex instructions is shown. A microprocessor includes an instruction queue, an instruction decoder, and a microcode controller. The instruction decoder is coupled to the instruction queue. The microcode controller is coupled to the instruction decoder and has a memory. The memory stores a combined microcode for M complex instructions arranged in a specific order, where M is an integer greater than 1. When the M complex instructions in the specific order have popped out of the first to M-th entries of the instruction queue, the instruction decoder operates the microcode controller to read the memory for the combined microcode with microcode reading trapping happened just once.