Interleaving Store Instructions Across Heterogeneous Processor Architectures
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Solution Overview
Problem
Existing digital signal processors (DSPs) face challenges in efficiently executing interleaving store instructions across processors with different register sizes and architectures, leading to inefficiencies in data processing and memory management.
Innovation Solution
A method and device are proposed that involve a first processor with a first set of registers and a second processor with a second set of registers, where the second set is larger. A translator generates a predication instruction to mask off select lanes of the second processor's registers, allowing for the execution of interleaving store instructions that emulate the functionality of a processor with a different architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a processor with larger register size is used, then data processing capacity is improved, but compatibility with processors of different architectures deteriorates
Solution Approach 1:
The patent uses software translation to create a virtual copy of the target processor architecture's register file. The translator emulates the smaller register architecture within the larger register structure, allowing code written for different architectures to execute on the current processor without modification. This copying approach preserves architecture compatibility while maintaining the benefits of larger register size.
Solution Approach 2:
The translator acts as an intermediary layer between the native processor architecture and the target architecture. It translates instructions from the target architecture into the native architecture's instruction set, enabling cross-architecture execution. This intermediary mechanism resolves the compatibility issue by providing a translation bridge without requiring architectural changes.
2Ease of manufacture
If register sizes differ between processors, then each processor is optimized for its specific architecture, but code portability between processors deteriorates
Solution Approach 1:
The translator enables the processor to perform multiple architectural functions by executing code from different architectures. The system maintains its native architecture optimization while simultaneously supporting foreign architectures through translation. This multi-functionality allows a single processor to serve multiple architectural ecosystems, improving code portability without sacrificing native optimization.
3Productivity
If interleaving store instructions are executed directly, then memory access efficiency is improved, but support across different processor architectures deteriorates
Solution Approach 1:
The translator creates a virtual copy of the target architecture's memory model and register file, including its specific interleaving store semantics. This virtual environment preserves the memory access efficiency of the target architecture while running on the source processor's hardware. The copied architecture maintains its optimized memory access patterns without requiring physical hardware changes.
Solution Approach 2:
The patent replaces the mechanical/hardware-based architecture with a software-based virtual architecture. Instead of physically implementing different register file sizes and memory hierarchies for different architectures, the system uses software translation to emulate these hardware characteristics. This substitution allows memory access efficiency to be preserved through software control rather than hardware implementation.
Data Source
AI summary
An example method includes generating a first interleave instruction based on compilation of a source file configured for execution by the first processor; generating a predication instruction to mask lane(s) of a first source register and a second source register of the second processor, in which the first source register stores a first vector and the second source register stores a second vector, based on translation of the source file; and generating a second interleave instruction based on compilation of the translated source file. The method further includes, based on the predication instruction and the second interleave instruction, reading respective portions of the first and second vectors from unmasked lanes of the first and second source registers, and interleaving the read portions to produce a third vector, which is then stored in a destination register of the second processor.