Memory Subsystem Program Suspend for Read Latency

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional memory sub-systems experience significant latency when handling mixed workloads with program and read operations due to the need to wait for program operations to complete, especially with longer programming times in devices like TLC or QLC memory, leading to increased controller memory requirements and costs.

Innovation Solution

Implementing a program suspend command to temporarily pause ongoing program operations on a shared wordline, allowing read operations to access data from the page cache without waiting for the program to finish, thereby reducing latency and eliminating the need for larger controller memories.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the system waits for program operations to complete before handling read operations on the same wordline, then data integrity is ensured, but read latency increases significantly

Engineering Contradiction:
Improvedata integrityVSAvoidread latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by checking the program status before executing read operations. The controller determines whether a program operation is ongoing on the target wordline before allowing a read operation to proceed. If the program is complete, the read operation is allowed to execute, thus avoiding unnecessary delays while ensuring data integrity when programs are in progress.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements dynamic control by adjusting read operation execution based on real-time program status. The system dynamically determines whether to allow or suspend read operations based on whether the program operation has completed, enabling flexible adaptation to changing memory states and optimizing both data integrity and read latency.

Inventive Principle:
Principle #15Dynamics

2Loss of time

If larger controller memory is used to buffer data during program operations, then read latency is reduced, but device cost and area increase

Engineering Contradiction:
Improveread latencyVSAvoidcontroller memory area
Core Design Contradiction:
Loss of timeVSArea of stationary object

Solution Approach 1:

The patent applies self-service by utilizing the memory device's own page cache to store read data during program operations, rather than requiring separate controller memory buffers. The memory device serves its own buffering needs by directing read operations to return data from its internal page cache, eliminating the need for additional controller memory capacity.

Inventive Principle:
Principle #25Self-service

3Loss of time

If program operations are suspended to allow read operations, then read latency decreases, but program operation completion time increases

Engineering Contradiction:
Improveread latencyVSAvoidprogram operation duration
Core Design Contradiction:
Loss of timeVSDuration of action of moving object

Solution Approach 1:

The patent checks program status before allowing read operations to proceed. By determining in advance whether a program operation is complete, the system can allow read operations without suspending programs, thereby avoiding the need to extend program duration while still enabling timely read access when programs are finished.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11698864B2Memory access collision management on a shared wordline
Publication Date: 2023.07.11 MICRON TECHNOLOGY INC
  • US11698864B2 patent drawing
  • US11698864B2 patent drawing
  • US11698864B2 patent drawing

AI summary

A processing device in a memory sub-system sends a program command to the memory device to cause the memory device to initiate a program operation on a corresponding wordline and sub-block of a memory array of the memory device. The processing device further receives a request to perform a read operation on data stored on the wordline and sub-block of the memory array, sends a suspend command to the memory device to cause the memory device to suspend the program operation, reads data corresponding to the read operation from a page cache of the memory device, and sends a resume command to the memory device to cause the memory device to resume the program operation.