Register Aliasing for SIMD Data Rearrangement
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Solution Overview
Problem
Existing data processing systems, such as those using SIMD and VFP processors, face inefficiencies due to the need for time-consuming data element rearrangement operations to align data within registers of varying sizes, which reduces the benefits of parallel processing.
Innovation Solution
The implementation of a register data store that allows data elements of different sizes to be accessed flexibly by specifying the data element size and register size in instructions, enabling mapping of registers to portions of the store based on size, thus allowing registers of differing sizes to be aliased and accessed without the need for extensive rearrangement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If data elements are arranged in fixed-size registers with predetermined positions, then data access is simplified, but time-consuming rearrangement operations are required to align data elements before SIMD processing
Solution Approach 1:
The patent implements dynamic register mapping where the register data store can be accessed with different register sizes and data element sizes specified by instructions. The mapping between registers and physical storage locations is dynamically adjusted based on the operation requirements, allowing data elements to be accessed directly in their natural positions without rigid fixed-size constraints. This dynamic approach eliminates the need for time-consuming rearrangement operations while maintaining ease of access.
Solution Approach 2:
The system allows instructions to specify different data element sizes and register sizes, changing the parameters of how data is interpreted and accessed. By allowing the data element size and register size to be variable parameters specified at instruction level, the system can directly access data elements in their stored positions without requiring rearrangement to fit fixed-size register templates. This parameter flexibility resolves the contradiction between access simplicity and rearrangement time.
2Productivity
If SIMD registers use fixed data element sizes, then processing operations are straightforward, but flexibility in accessing data elements of different sizes is reduced
Solution Approach 1:
The patent creates a universal register data store that can serve multiple functions by accepting different data element sizes and register sizes specified in instructions. The same register data store infrastructure handles both fixed-size and variable-size data elements, and the same processing logic operates on different data formats. This multi-functionality maintains parallel processing efficiency while adding flexibility in data element size handling.
Solution Approach 2:
The system dynamically adapts the register interpretation based on instruction specifications. When an instruction specifies a particular data element size and register size, the register data store dynamically adjusts its mapping and access pattern accordingly. This dynamic behavior allows the system to maintain efficient parallel processing for each specific data size while being versatile across different data sizes, resolving the contradiction between productivity and adaptability.
3Measurement precision
If separate registers are provided for different data element sizes, then data access is precise, but device complexity and overhead increase
Solution Approach 1:
The patent merges multiple separate register concepts into a single unified register data store. Instead of providing separate physical registers for different data element sizes, the system combines them into one register data store that can be accessed with different size specifications. The instruction set specifies data element size and register size parameters that control how the unified store is interpreted and accessed. This merging maintains precise data element access while reducing device complexity by eliminating redundant separate register structures.
4Reliability
If data rearrangement operations are performed to align data elements, then correct processing alignment is achieved, but code density and execution speed are reduced
Solution Approach 1:
The system performs preliminary organization of data elements in the register data store during data loading and storage operations, arranging data elements in positions that are naturally accessible for their specific sizes. When processing occurs, the data is already in the correct alignment positions, eliminating the need for rearrangement operations before processing. This preliminary action ensures correct alignment while maintaining execution speed, as no additional rearrangement steps are needed.
Solution Approach 2:
The patent extracts the data rearrangement requirement from the processing pipeline by allowing direct access to data elements in their natural stored positions. The instruction system specifies data element size and register size to directly access elements without requiring extraction and repositioning operations. This extraction of the rearrangement step maintains alignment correctness while improving execution speed by eliminating unnecessary operations.
Data Source
AI summary
A register data store 20 is provided within a data processing system 2. The register data store 20 may be accessed via registers for which a data processing instruction specifies a register size Q, D and a data element size S16, S8 for the multiple SIMD data elements to be manipulated by that data processing instruction. A given data processing element may be accessed via different registers depending upon the mapping between the register specifier, the register size and the data element size to a particular location within the register data store 20.