Vector Four-Fundamental-Rule Operation Unit for Flexible Data Width Support
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Solution Overview
Problem
Current computer technologies face performance bottlenecks in vector four-fundamental-rule operations due to limited inter-chip communication, insufficient on-chip cache, and inflexible support for vectors of different lengths during calculations, particularly in machine learning algorithms.
Innovation Solution
A vector four-fundamental-rule operation device comprising a storage unit, register unit, and vector four-fundamental-rule operation unit that temporarily stores vector data in a scratchpad memory, allowing flexible support for vectors of varying lengths and improving execution performance by optimizing data storage and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple general-purpose processors are adopted for parallel execution, then operation performance is improved, but intercommunication bottleneck occurs
Solution Approach 1:
The patent merges multiple processing elements into a unified vector processing architecture where a single processor executes vector instructions operating on multiple data elements simultaneously. This eliminates the intercommunication overhead between multiple processors while maintaining parallel processing capability through SIMD (Single Instruction Multiple Data) execution, directly resolving the contradiction between improved performance and reduced communication complexity.
2Productivity
If GPU is adopted for vector calculation, then operation performance is improved, but off-chip bandwidth becomes bottleneck
Solution Approach 1:
The patent transitions from scalar processing to vector processing by adding a dimension of data parallelism. Instead of processing one data element at a time through multiple sequential operations, the system processes multiple data elements simultaneously in a single instruction cycle, thereby improving performance without proportionally increasing off-chip memory access requirements.
3Productivity
If specialized vector operation device is adopted, then operation performance is improved, but flexibility for different vector lengths is reduced
Solution Approach 1:
The patent implements dynamic vector length support through configurable processing elements and flexible memory addressing. The vector processing unit can adapt its operation to handle vectors of varying lengths by dynamically adjusting the number of active processing elements and memory access patterns, thereby maintaining both high performance and flexibility without requiring fixed architecture constraints.
Data Source
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AI summary
A device and a method for performing a vector four-fundamental-rule operation are provided, which are configured to perform a vector four-fundamental-rule operation according to a corresponding instruction set. The device includes a storage unit, a register unit, and a vector four-fundamental-rule operation unit. The storage unit is configured to store vectors; the register unit is configured to store addresses where the vectors are stored; the vector four-fundamental-rule operation unit is configured to acquire vector addresses from the register unit according to the corresponding instruction set, to acquire vectors from the storage unit according to the vector addresses acquired, and to perform the vector four-fundamental-rule operation on the vectors acquired to obtain a result of the vector four-fundamental-rule operation. According to the disclosure, vector data involved in calculation can be temporarily stored into a scratchpad memory, so that vector data of different widths can be supported more flexibly and effectively in a vector four-fundamental-rule operation process, thereby improving the performance of executing a large number of vector four-fundamental-rule operations.