Microprocessor History Buffer Bypass for Register File Hazards
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Solution Overview
Problem
High-performance processors face challenges in maintaining accurate processor state due to incorrect assumptions about instruction results, leading to interruptions and recovery needs, especially in multi-execution slice architectures where instructions are processed concurrently.
Innovation Solution
A method is introduced where at least a first and a second instruction are dispatched in a single processing cycle targeting the same register file entry, with the first result data being written directly into a history buffer if it is older than the second result data, and the second result data being written into the register file entry, utilizing multiple processing slices with history buffers and register files.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple instructions are dispatched in parallel targeting the same register file entry, then processor productivity is improved, but processor state reliability deteriorates due to incorrect assumptions about instruction results
Solution Approach 1:
The patent applies preliminary action by checking the age of result data before writing to the register file. The completion stage performs a preliminary check to determine if the result data is older than the instruction being completed, preventing incorrect state updates before they occur. This advance verification resolves the contradiction by ensuring reliability checks are performed before parallel productivity operations could cause errors.
Solution Approach 2:
The patent introduces an intermediary mechanism in the completion stage that mediates between the parallel execution units and the register file. This intermediary checks the age of result data and controls when writes to the register file occur, preventing incorrect assumptions from corrupting the processor state while allowing parallel instructions to proceed. The intermediary resolves the contradiction by filtering out potentially harmful parallel writes.
2Loss of time
If result data is written directly into history buffer bypassing register file, then timing penalty is reduced, but device complexity increases
Solution Approach 1:
The patent extracts the timing-critical path from the register file lookup by allowing result data to be written directly to the history buffer, bypassing the register file for older data. This extraction removes the timing penalty from the critical path while maintaining correctness through the completion stage's age checking. The complexity increase is acceptable because it only affects the history buffer management path, not the core execution path.
Data Source
AI summary
Method and system for writing a history buffer in a processing unit is provided. At least a first instruction and a second instruction are dispatched in a single processing cycle, targeting a same register file entry. The processing unit includes two or more processing slices, each processing slice comprising a corresponding history buffer and at least a portion of a register file. Upon determining that first result data corresponding to the first instruction is older than second result data corresponding to the second instruction, the first result data is written into a history buffer bypassing the register file entry, in response to the determination. Further, the second result data is written into the register file entry.