Processor Trace Control System Bandwidth Reduction
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Solution Overview
Problem
In multi-core systems, the high bandwidth required for trace data transmission becomes a challenge due to increased bandwidth needs with the number of processors, especially in systems-on-chip where external memory interfaces are absent, making traditional bus trace methods ineffective.
Innovation Solution
A control system comprising a central processor and a trace processor, connected via an inter-processor bus, uses specific instructions like STORE_FULL_TRACE and STORE_NO_TRACE to selectively trace operations, reducing bandwidth requirements by filtering data and only transmitting essential trace data through a trace interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If traditional bus trace methods are used in multi-core systems, then complete trace data can be captured, but bandwidth requirements increase significantly
Solution Approach 1:
The patent extracts only the essential trace data that needs to be transmitted to external debugging equipment. Instead of transmitting all trace data from multiple processors, the system selectively extracts and transmits only the necessary information, thereby reducing bandwidth consumption while maintaining trace data completeness for debugging purposes.
Solution Approach 2:
The patent segments the trace data transmission by introducing a trace manager component that selectively controls what data is transmitted. The trace manager divides the trace data stream and filters out non-essential information, allowing complete trace capability while reducing the actual bandwidth used for transmission.
2Quantity of substance
If external memory interfaces are used for trace data storage, then sufficient storage capacity is available, but systems-on-chip cannot accommodate external interfaces
Solution Approach 1:
The patent merges the trace data storage functionality directly into the processor system by providing each processor with local trace data storage resources. This eliminates the need for external memory interfaces while ensuring sufficient storage capacity is available within the system-on-chip architecture itself.
Solution Approach 2:
The patent transitions from external storage architecture to internal storage architecture by allocating trace data storage resources within the processor boundaries. This dimensional change from external to internal storage eliminates complex external interfaces while maintaining adequate storage capacity through integrated memory resources.
3Loss of information
If all processors transmit trace data simultaneously, then complete system behavior is captured, but bandwidth requirements become unmanageable
Solution Approach 1:
The patent introduces a trace manager as an intermediary component that coordinates trace data transmission from multiple processors. The trace manager selectively receives and transmits trace data from different processors based on debugging needs, ensuring complete system behavior coverage while managing bandwidth consumption through controlled, non-simultaneous transmission.
Solution Approach 2:
The patent implements periodic or selective trace data transmission from different processors rather than simultaneous continuous transmission. The trace manager controls the timing and selection of trace data from each processor, allowing complete system behavior to be captured over time while keeping instantaneous bandwidth requirements manageable.
Data Source
AI summary
A method includes invoking a first instruction that, when executed by a first processor, causes the first processor to perform a first operation, and that, when executed by the first processor, causes a second processor to perform a second operation. The method further includes a second instruction that, when executed by the first processor, causes the first processor to perform the first operation while causing the second processor to perform a third operation or while leaving the second processor unaffected. A control system includes a first processor and a second processor, wherein the first processor is configured to execute a first instruction to perform a first operation, wherein the second processor is configured to perform a second operation when the first processor executes the first instruction.