Multi-port Register File with Pipelined Write and Asynchronous Read
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Solution Overview
Problem
Multi-port register files face challenges in reducing write time and area efficiency due to buffering and pipelining requirements, which can lead to increased area and power consumption, especially when data forwarding is involved during asynchronous reads.
Innovation Solution
Implementing a dual-port or four-port register file architecture with synchronous and pipelined write ports and asynchronous read ports, where data is written to pipelined registers first and then transferred to memory array registers, allowing for data forwarding when read and write addresses match, thereby reducing write time and area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If pipelining is implemented to reduce write time, then write speed is improved, but area increases
Solution Approach 1:
The register file is segmented into two distinct parts: pipelined registers for write operations and memory array registers for storage. This segmentation allows the pipelined registers to handle write operations efficiently without requiring the entire register file to be pipelined, thus improving write speed while controlling area increase.
Solution Approach 2:
Pipelined registers act as an intermediary between the write input and the memory array registers. Data is first written to the pipelined registers and then transferred to the memory array registers, enabling faster write operations while the pipelined registers serve as a buffer that doesn't significantly increase the overall area.
2Adaptability or versatility
If multiple ports are added to increase functionality, then adaptability is improved, but area increases quadratically
Solution Approach 1:
The register file architecture is designed to support multiple ports with different functions (read ports and write ports) sharing the same memory array structure. The pipelined registers provide universal buffering capability for both read and write operations, allowing the system to achieve multi-functionality without requiring separate dedicated structures for each port type, thus controlling area growth.
3Speed
If data forwarding is implemented during asynchronous reads, then read speed is improved, but complexity increases
Solution Approach 1:
Data is prepared in advance in the pipelined registers before the actual read operation completes. When an asynchronous read occurs and the read address matches the write address, the data is already available in the pipelined registers, allowing immediate forwarding without requiring complex real-time detection and preparation logic.
Solution Approach 2:
The pipelined registers automatically provide data forwarding capability when read and write addresses match, without requiring external control logic. The system self-determines when data forwarding is applicable and handles the data transfer autonomously, reducing the complexity of additional control mechanisms.
Data Source
AI summary
In an embodiment of the invention, a multi-port register file includes write port inputs (e.g. write address, write enable, data input) that are pipelined and synchronous and read port inputs (e.g. read address) that are asynchronous and are not pipelined. Because the write port inputs are pipelined, they are stored in pipelined registers. When data is written to the multi-port register file, data is first written to the pipelined registers during a first clock cycle. On the next clock cycle, data is read from the pipelined registers and written into memory array registers. When the read address is identical to the write address stored in the pipelined memory, the result of a bit-wise ANDing of data stored in pipelined synchronous data registers and data stored in pipelined synchronous bit-wise registers is presented at the output of the multi-port register file.