Non-Stalling GPU Register File with Work-Order Hopper
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Solution Overview
Problem
Conventional GPUs face challenges in maintaining low power consumption while processing large quantities of data in parallel, which is crucial for hand-held devices, as they tend to consume significant power and require efficient data management to avoid stalling processes.
Innovation Solution
The GPU system incorporates a non-stalling processing engine that uses a large static random access memory (SRAM) to store and manage data, allowing efficient data exchange with potentially stalling processes, and employs a work-order message system to route data between processing units, reducing the need for skid buffers and flip-flops, thereby minimizing power consumption and storage space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If large quantities of data are moved between different portions of the system to support highly parallel processing, then processing capability is improved, but power consumption increases
Solution Approach 1:
The system segments data storage into multiple register files (first register file and second register file) that can be independently managed. This allows data to be organized and accessed in smaller, more efficient units, reducing the power required to move and manage large quantities of data across the entire system while maintaining parallel processing capabilities.
Solution Approach 2:
The patent introduces a work-order hopper as an intermediary structure between the processing elements and the register files. This hopper manages data flow and routing, allowing efficient data movement without requiring full system-wide data transfers, thereby reducing power consumption while supporting high parallel processing throughput.
2Productivity
If data is stored in conventional memory structures to support parallel processing, then data availability is improved, but chip area increases
Solution Approach 1:
The patent merges the functionality of multiple register files with the work-order hopper structure, creating an integrated system where data storage and data management are combined. This consolidation reduces the total chip area required compared to having separate, dedicated memory structures for each function, while still providing adequate data availability for parallel processing operations.
Solution Approach 2:
The register files are designed to serve multiple purposes: storing data for active processing, holding data for stalled operations, and providing data to multiple processing elements simultaneously. This multi-functionality reduces the need for dedicated memory structures for each purpose, thereby reducing overall chip area while maintaining data availability.
3Reliability
If skid buffers and flip-flops are used to manage data flow between processing units, then data transfer reliability is improved, but power consumption and chip area increase
Solution Approach 1:
The patent extracts the essential data management functionality from traditional skid buffers and flip-flops, implementing only the necessary data routing and storage capabilities within the work-order hopper and register file system. This selective extraction maintains data transfer reliability by implementing only the critical functions, while eliminating redundant components that would increase power consumption and chip area.
Data Source
AI summary
A graphics processing unit may include a register file memory, a processing element (PE) and a load-store unit (LSU). The register file memory includes a plurality of registers. The PE is coupled to the register file memory and processes at least one thread of a vector of threads of a graphical application. Each thread in the vector of threads are processed in a non-stalling manner. The PE stores data in a first predetermined set of the plurality of registers in the register file memory that has been generated by processing the at least one thread and that is to be routed to a first stallable logic unit that is external to the PE. The LSU is coupled to the register file memory, and the LSU accesses the data in the first predetermined set of the plurality of registers and routes to the first stallable logic unit.