NoC Overlay Layer for Multicore Processor Data Isolation

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Solution Overview

Problem

In multicore processors, the efficient execution of complex computations is hindered by the complexity of data movement and memory management across processing cores, which requires significant computational resources and complicates programming, especially for higher-level programming languages.

Innovation Solution

A NoC overlay layer is introduced to logically isolate the computation layer from the NoC layer, automating data flow management and simplifying memory management tasks, allowing the computation layer to focus on computations while the overlay layer handles data transfer and communication tasks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data movement and memory management are handled directly by the computation layer in traditional NoC architectures, then the system can execute complex computations across multiple cores, but the computational resources are significantly consumed by communication overhead and programming complexity increases

Engineering Contradiction:
Improvecomputation execution efficiencyVSAvoidprogramming complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces an overlay layer as an intermediary between the computation layer and the physical NoC layer. This overlay layer provides abstraction mechanisms including virtual addresses, buffered communication, and automated data movement management, thereby reducing programming complexity while maintaining computation productivity

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the system into distinct layers: computation layer, overlay layer, and physical NoC layer. Each layer has specific responsibilities and interfaces, allowing independent optimization and reducing the complexity burden on the computation layer by offloading communication management to the overlay layer

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If multiple memory copy operations are issued to transmit larger amounts of data between cores, then the data transfer capacity increases, but the computational overhead and time required for management increases

Engineering Contradiction:
Improvedata transfer volumeVSAvoiddata management time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The overlay layer performs preliminary actions by pre-establishing communication paths, pre-buffering data, and pre-managing memory allocation before actual data transfer occurs. This reduces the time required during actual computation by having communication management prepared in advance

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The overlay layer enables continuous data transfer operations by implementing buffered communication and automated retransmission mechanisms, allowing data to be transferred continuously without interruption for management tasks, thereby reducing total management time while increasing effective data transfer volume

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS11467846B2Overlay layer for network of processor cores
Publication Date: 2022.10.11 TENSTORRENT AI ULC
  • US11467846B2 patent drawing
  • US11467846B2 patent drawing
  • US11467846B2 patent drawing

AI summary

Methods and systems related to the efficient execution of complex computations by a multicore processor and the movement of data among the various processing cores in the multicore processor are disclosed. A multicore processor stack for the multicore processor can include a computation layer, for conducting computations using the processing cores in the multicore processor, with executable instructions for processing pipelines in the processing cores. The multicore processor stack can also include a network-on-chip layer, for connecting the processing cores in the multicore processor, with executable instructions for routers and network interface units in the multicore processor. The computation layer and the network-on-chip layer can be logically isolated by a network-on-chip overlay layer.