Register Access Optimization via Execution Unit Merging

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Solution Overview

Problem

The performance of computing systems is hindered by slow buses when accessing devices with multiple registers, leading to inefficient batch operations and reduced system performance due to frequent access to registers with multiple storage units.

Innovation Solution

A method and system that create an instruction set for accessing devices connected to a CPU via a bus, where multiple execution units are merged and optimized when corresponding to the same operation request and register address, reducing the number of accesses by generating optimized execution units and sending them to the bus.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple execution units with the same operation request and register address are generated, then the completeness of register configuration is improved, but the number of bus accesses increases and system performance deteriorates

Engineering Contradiction:

Improveregister configuration completenessVSAvoidsystem performance

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent merges multiple execution units that have the same operation request and register address into a single optimized execution unit. This is achieved by detecting duplicate execution units and consolidating them, thereby reducing the number of bus accesses while maintaining the completeness of register configuration. The merging process preserves the relative order of instructions and ensures all necessary register configurations are still performed.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent performs preliminary detection and optimization of execution units before they are sent to the bus. By pre-identifying and merging duplicate execution units with the same operation request and register address, the system reduces the number of accesses that will occur on the bus, thereby improving system performance while maintaining configuration completeness.

Inventive Principle:

Principle #10Preliminary action

2Adaptability or versatility

If frequent accesses are made to registers with multiple storage units, then the flexibility of batch operations is improved, but the bus load increases and system performance deteriorates

Engineering Contradiction:

Improvebatch operation flexibilityVSAvoidsystem performance

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent combines multiple access operations to the same register address into single optimized execution units. This merging approach maintains the flexibility needed for batch operations on registers with multiple storage units while significantly reducing the frequency of bus accesses, thereby improving system performance.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent creates optimized execution units that replicate the functionality of multiple original execution units but with reduced access frequency. By copying and consolidating the operation logic into fewer, more efficient execution units, the system maintains batch operation flexibility while reducing bus load.

Inventive Principle:

Principle #26Copying

3Productivity

If execution units are merged and optimized, then the number of bus accesses is reduced and system performance is improved, but the complexity of instruction processing increases

Engineering Contradiction:

Improvesystem performanceVSAvoidinstruction processing complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent performs the complex detection and merging of execution units as a preliminary action before bus access. By pre-processing and optimizing execution units in advance, the system consolidates complexity into a single processing stage, thereby improving system performance without significantly increasing the complexity of the overall instruction processing pipeline.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20250004761A1Method and system for accessing registers of a device

Publication Date: 2025.01.02 MONTAGE TECHNOLOGY CO LTD

AI summary

In a method and a system for accessing registers of a device, the device is connected to a CPU via a bus and includes multiple registers, each corresponding to a different address. Each register includes one or more storage units which share a register address. The access method includes: creating an instruction set for accessing the device; in response to operation requests from the CPU to the device, selecting corresponding instructions from the instruction set, to generate execution units with the minimum execution granularity corresponding to the operation requests; detecting the execution units, and when detecting that there are multiple execution units corresponding to the same type of operation request and multiple execution units includes multiple instructions of the same type corresponding to the same register address, merging and optimizing the multiple execution units to generate optimized execution units, and sending the optimized execution units to the bus.