Logical Register Mapper Eviction for Wide Data Width Instructions
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Solution Overview
Problem
Current data processing systems face latency issues when processing wide data width instructions, such as matrix-multiply-add (MMA) instructions, due to insufficient port bandwidth in logical register mappers and history buffers, leading to increased silicon usage, power consumption, and timing constraints.
Innovation Solution
The implementation of a processor architecture that includes a main register file, an accumulator register file, a logical register mapper, and a history buffer, where multiple main register file entries are mapped to a single accumulator register file entry, allowing for efficient processing of wide data width instructions by using a single read port in the logical register mapper and a single write port in the history buffer, reducing the need for additional ports and cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple target registers are renamed and evicted from the logical register mapper to the history buffer to accommodate wide data width instructions, then the processor can process MMA instructions, but the port bandwidth is insufficient causing processor latency
Solution Approach 1:
The patent segments the register renaming process by identifying and renaming only the primary target register (VSR0) instead of all four target registers (VSR0-VSR3). This segmentation reduces the number of rename operations from four to one, thereby reducing the bandwidth requirements of the logical register mapper and history buffer ports while still enabling MMA instruction processing.
Solution Approach 2:
The patent extracts only the essential rename operation needed for MMA instructions - specifically the primary target register VSR0 - and leaves the other target registers (VSR1-VSR3) unchanged. This extraction approach eliminates unnecessary rename operations that would consume port bandwidth, resolving the bandwidth insufficiency problem while maintaining MMA functionality.
2Productivity
If the number of logical register mapper target read ports and history buffer write ports is increased to accommodate MMA instructions, then processing throughput improves, but silicon usage increases
Solution Approach 1:
The patent segments the register file into a main register file (containing VSR0-VSR3) and an accumulator register file, and segments the renaming operation to affect only VSR0. This segmentation allows MMA instructions to be processed using a single read port and single write port, avoiding the need to increase port count and thus avoiding increased silicon usage.
3Productivity
If the number of read ports and write ports is increased to process wide data width instructions, then computational throughput improves, but power consumption increases
Solution Approach 1:
The patent segments the register renaming function to operate only on the primary target register VSR0, reducing the number of active ports from multiple to just one read port and one write port. This segmentation maintains computational throughput for MMA instructions while significantly reducing power consumption by minimizing the number of active port operations.
Data Source
AI summary
A computer system, processor, programming instructions and/or method of processing data that includes a main register file having a plurality of entries for storing data; an accumulator register file having a plurality of entries for storing data wherein multiple main register file entries are mapped to one accumulator register file entry in the at least one accumulator register file; a logical register mapper to track and map logical registers to main register file entries, and a history buffer. Processing wide data width instructions includes evicting and restoring information from a single primary entry in the logical register mapper through a single read or write port in the logical register mapper without evicting or restoring the remaining other multiple main register file entries mapped in the accumulator register.