Endian Agnostic SIMD Load Store Unit Architecture
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Solution Overview
Problem
Current processor architectures face complexity in managing data operations across big and little endian modes, requiring different instructions for various data element sizes and leading to inefficiencies in SIMD operations and increased opcode space usage.
Innovation Solution
A processor system that supports both big and little endian modes with a single load instruction and single store instruction, which are insensitive to data element size, using an instruction set architecture (ISA) that determines data element size and endian mode to perform SIMD operations efficiently, and includes execution units that align data based on endian mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If different instructions are used for various data element sizes in SIMD operations, then data operations can be performed accurately, but the opcode space complexity increases and instruction variety increases
Solution Approach 1:
The patent applies universality by designing a single load instruction and a single store instruction that can handle multiple data element sizes (bytes, halfwords, words, doublewords) without requiring separate instructions for each size. The instruction decodes to a universal format that accommodates different element sizes through a single opcode, eliminating the need for multiple variant instructions and reducing opcode space complexity while maintaining accurate data operations.
2Reliability
If byte reordering is performed during loading and storing in bi-endian processors, then correct endian mode operation is achieved, but processing time increases and operation complexity increases
Solution Approach 1:
The patent applies preliminary action by performing endian mode detection and data arrangement in advance during the instruction decode phase, before the actual load or store operation executes. The universal load/store instruction decodes to determine the current endian mode and pre-arranges the data element ordering accordingly, so that when the data is transferred to or from memory, no additional byte reordering is needed during the critical data path operation, thus reducing processing time.
3Adaptability or versatility
If multiple variant instructions are provided for different endian modes and data sizes, then complete control over data handling is achieved, but the number of instructions increases and ease of operation decreases
Solution Approach 1:
The patent merges multiple instruction variants into a single universal load instruction and a single universal store instruction. Instead of providing separate instructions for different endian modes (big-endian, little-endian) and different data sizes, the patent combines these functions into one instruction that automatically adapts to the current endian mode and data element size through its universal decode format, significantly simplifying instruction usage while maintaining complete control over data handling.
Data Source
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AI summary
A processor includes a register and a load store unit (LSU). The LSU loads data into the register from a memory. When in little endian mode, bytes from sequentially increasing memory addresses are loaded in order of corresponding sequentially increasing byte memory addresses from a first end (right end) of the register to a second end (left end) of the register. When in big endian mode, bytes from sequentially increasing memory addresses are loaded in order of corresponding sequentially increasing memory addresses from the second end (left end) of the register to the first end (right) of the register. Therefore, regardless of operating in little or big endian mode, the data in the register has its most significant byte on its left side and its least significant byte on its right side. Endian-sensitive SIMD instructions require byte re-ordering of register data, according to element size, for correct execution.