Unified Decoder for Divergent Register Addressing
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Solution Overview
Problem
Data processing systems supporting multiple instruction sets face increased circuit resources and power consumption due to the need for separate mechanisms for register addressing, which is inefficient when architectural registers are addressed differently by various instruction sets.
Innovation Solution
The implementation of dual decoder circuitry that maps logical register specifiers from different instruction sets to a common address format, allowing shared processing circuitry to reduce circuit overhead and power consumption, with divergent mappings ensuring some values map to different architectural registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate mechanisms are provided for register addressing in different instruction sets, then the ability to support divergent addressing modes is improved, but circuit resources and power consumption increase
Solution Approach 1:
The patent implements a universal register addressing mechanism that handles multiple instruction sets (ARM and Thumb) through a single unified decoder. The decoder uses a common mapping scheme where register specifiers from both instruction sets are translated to the same architectural register indices, allowing the same hardware circuitry to serve multiple instruction set architectures without requiring separate decoding paths.
Solution Approach 2:
The patent merges the register addressing mechanisms for ARM and Thumb instruction sets into a single unified decoder unit. Instead of maintaining separate decoders for each instruction set, the invention combines them into one shared component that handles register specifiers from both instruction sets using a common mapping approach, thereby reducing overall circuit complexity and resource usage.
2Adaptability or versatility
If separate mechanisms are provided for register addressing in different instruction sets, then the ability to support divergent addressing modes is improved, but power consumption increases
Solution Approach 1:
The unified decoder serves multiple instruction sets with a single hardware implementation, eliminating the need for parallel decoder circuits. This multi-functional approach ensures that the same circuitry processes register specifiers from both ARM and Thumb instruction sets, significantly reducing power consumption compared to having separate dedicated decoders for each instruction set.
Solution Approach 2:
By merging the register addressing functionality into a single decoder unit, the patent reduces the total power consumption associated with register decoding operations. The combined decoder processes instructions from both instruction sets through shared hardware resources, avoiding the redundant power consumption that would result from maintaining separate decoding mechanisms.
3Device complexity
If a common address format is used with divergent mappings, then circuit overhead is reduced, but the mapping complexity between logical and architectural registers increases
Solution Approach 1:
The patent applies different mapping strategies for different instruction sets within the unified decoder. The ARM instruction set uses one mapping scheme while the Thumb instruction set uses another, allowing each instruction set to be optimized independently while still converging to a common address format. This local differentiation within a global unity approach manages mapping complexity effectively.
Solution Approach 2:
The unified decoder acts as an intermediary that translates logical register specifiers from both instruction sets into architectural register indices using a common address format. This intermediary component absorbs the mapping complexity internally while presenting a simplified interface to the rest of the processor, effectively managing the complexity without exposing it to other parts of the system.
Data Source
AI summary
A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file 18 containing architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some values of those logical registers specifiers correspond to different architectural registers within the architectural register file 18. A first decoder 4 for the first instruction set and a second decoder 6 for the second instruction set serve to decode the logical register specifiers to a common register addressing format. This common register addressing format is used to supply register specifiers to renaming circuitry 10 for supporting register renaming in conjunction with a physical register file 16 and an architectural register file 18.