High-Word Facility Extending General Purpose Registers
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Solution Overview
Problem
Current computer systems face limitations in the number of general-purpose registers available to instructions, which restricts the functionality and performance of software, especially in architectures like IBM z/Architecture, where the number of 64-bit registers is not fully utilized in 32-bit mode, leading to inefficiencies in memory addressing and operand handling.
Innovation Solution
The High-Word Facility extends the effective number of general-purpose registers by allowing instructions to access the high word of 64-bit registers in 32-bit mode, providing new instructions that manipulate the hidden high bits, effectively doubling the number of 32-bit registers available for applications, thereby enhancing memory addressing and operand handling capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the computer system uses 64-bit registers in 32-bit mode, then the register width is sufficient for future scalability, but the effective number of available registers is limited
Solution Approach 1:
The 64-bit register is segmented into two separate 32-bit registers (low-order and high-order halves). Instructions can selectively access either the low-order half (traditional R0-R31) or the high-order half (extended R0-R31), effectively doubling the available register count while maintaining backward compatibility with 32-bit software.
Solution Approach 2:
The patent adds a new dimension to register access by introducing high-order register fields in instruction formats. This allows software to access the upper 32 bits of 64-bit registers, creating an extended register space that perpendicular to the traditional register addressing mode.
2Adaptability or versatility
If the system provides more general-purpose registers, then software functionality and performance improve, but the instruction format complexity increases
Solution Approach 1:
The instruction format dynamically adapts based on the register field encoding. When high-order register fields are present and non-zero, the system interprets them as extended register references; otherwise, it uses traditional register addressing. This dynamic interpretation allows the same instruction format to support both traditional and extended register modes.
Solution Approach 2:
The high-order register field acts as an intermediary that bridges traditional 32-bit software and extended register capabilities. By using this intermediate field, the system can encode extended register references without fundamentally changing the basic instruction format structure, thus managing complexity while providing enhanced functionality.
3Ease of operation
If the system uses traditional 32-bit register mode, then compatibility with existing software is maintained, but memory addressing and operand handling efficiency is reduced
Solution Approach 1:
The system provides self-service by automatically managing the transition between traditional and extended register modes. The high-order register fields are transparently handled by the instruction decoder, which automatically interprets them as extended register references when present, requiring no changes to existing software while enabling improved performance when the extended register space is utilized.
Data Source
AI summary
A computer employs a set of General Purpose Registers (GPRs). Each GPR comprises a plurality of portions. Programs such as an Operating System and Applications operating in a Large GPR mode, access the full GPR, however programs such as Applications operating in Small GPR mode, only have access to a portion at a time. Instruction Opcodes, in Small GPR mode, may determine which portion is accessed.