Load-Store Device Strided Address Generator Parallel Memory Access
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Solution Overview
Problem
Existing vector strided operations in electronic circuits require multiple iterations to access data elements at different memory addresses, leading to inefficiencies in data access and processing.
Innovation Solution
A processor and load-store device with a strided address generator and load-store circuit that enables simultaneous access to multiple data elements at discrete addresses in memory, using a vector register file to accelerate strided operations by generating and processing addresses based on a base address and stride.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If one access address is generated at a time according to the related art, then the access operation can be performed sequentially, but the number of iterations required to access n target data elements increases to n iterations
Solution Approach 1:
The patent segments the address generation process by dividing it into multiple parallel address generation units, each capable of generating an access address independently. This allows multiple data elements to be accessed simultaneously in parallel, reducing the total number of iterations required from n to 1 or a small constant number, thereby significantly improving productivity while minimizing time loss.
2Productivity
If multiple data elements are accessed in a single iteration, then the strided operation is accelerated, but the device complexity increases due to the need for parallel address generation
Solution Approach 1:
The patent introduces an intermediary component, the stride multiplier, which receives a base address and stride value, then generates multiple strided addresses in parallel. This intermediary simplifies the overall system architecture by centralizing the complex address generation logic in a dedicated unit, rather than distributing complexity across multiple independent address generation circuits, thus achieving high productivity with controlled device complexity.
3Productivity
If n iterations are performed to access n data elements, then each access operation can be completed sequentially, but the overall data processing efficiency decreases
Solution Approach 1:
The patent implements continuous useful action by enabling parallel data access operations where multiple data elements are fetched from memory simultaneously in a single iteration. The load-store circuit is designed to handle multiple memory addresses in parallel, ensuring that the data processing pipeline remains continuously active without idle iteration cycles, thereby maximizing productivity and minimizing total execution time.
Data Source
AI summary
A processor, an operation method, and a load-store device are provided. The processor is adapted to access a memory. The processor includes a vector register file (VRF) and the load-store device. The load-store device is coupled to the VRF. The load-store device performs a strided operation on the memory. In a current iteration of the strided operation, the load-store device reads a plurality of first data elements at a plurality of discrete addresses in the memory and writes the first data elements into the VRF, or the load-store device reads a plurality of second data elements from the VRF and writes the second data elements into a plurality of discrete addresses in the memory during the current iteration of the strided operation.