Register Mapping for Multi-Instruction Set Processor Interoperability
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Solution Overview
Problem
Data processing systems supporting multiple instruction sets face challenges in efficiently sharing register resources, as different instruction sets often operate on architectural registers of varying widths, limiting interoperability and increasing circuit resource requirements.
Innovation Solution
A one-to-one mapping between register specifiers of different instruction sets allows for shared use of registers, enabling access to all values stored by one instruction set from another, with embodiments using 2N-bit registers to facilitate manipulation of 2N-bit data values and incorporating banked registers for rapid exception processing and efficient decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate registers are provided for each instruction set, then each instruction set can operate independently, but circuit resource requirements increase
Solution Approach 1:
The patent implements a universal register file that serves multiple instruction sets (ARM and Thumb) simultaneously. The register specifiers from both instruction sets map to the same physical register resources, allowing a single register file to handle operations from different instruction sets without requiring separate dedicated registers for each architecture.
Solution Approach 2:
The patent merges the register resources of ARM and Thumb instruction sets into a unified register file. By combining the previously separate register allocations into a shared resource pool with systematic mapping between the two instruction set architectures, the design reduces overall circuit complexity while maintaining full functionality for both instruction sets.
2Adaptability or versatility
If different data widths are used for different instruction sets, then each instruction set can optimize for its native format, but interoperability between instruction sets deteriorates
Solution Approach 1:
The patent introduces a mapping mechanism that acts as an intermediary between ARM and Thumb instruction sets. This mapping layer translates register specifiers from one instruction set format to the corresponding specifiers in the other format, enabling seamless interoperability and data sharing between programs written in different instruction sets while preserving their native data width optimizations.
Solution Approach 2:
The patent employs parameter changes by systematically transforming register specifier parameters between different instruction set architectures. The mapping relationships adjust the register number parameters according to the specific architecture being accessed, allowing the same physical register to be addressed correctly whether accessed through ARM or Thumb instruction sequences.
3Ease of operation
If a one-to-one mapping between register specifiers is implemented, then interoperability between instruction sets improves, but decoding complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-establishing systematic mapping relationships between ARM and Thumb register specifiers. These mapping tables and relationships are constructed in advance during processor design and initialization, allowing the decoder to efficiently translate register specifiers without complex runtime analysis, thereby reducing actual decoding complexity despite the comprehensive mapping coverage.
Data Source
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AI summary
A processor (4) is provided which supports a first instruction set specifying 32-bit architectural registers and a second instruction set specifying 64-bit architectural registers. Each of these instruction sets is presented with its own set of architectural registers for use. The first set of registers presented to the first instruction set has a one-to-one mapping to the second set of registers presented to this second instruction set. The registers which are provided in hardware are 64-bit registers. In some embodiments, when executing program instructions of the first instruction set, only the least significant portion of these 64-bit registers are accessed and manipulated with the remaining most significant portion of the registers being left unaltered. Register specifying fields within instructions of the first instruction set are decoded together with a current exception mode to determine which architectural register to use whereas the second instruction set uses register specifying fields without a dependence upon exception mode to determine which architectural register are to be used.